| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonConstPropagation.cpp | 623 Register DefR(MD); in visitPHI() local
624 assert(TargetRegisterInfo::isVirtualRegister(DefR.Reg)); in visitPHI()
629 if (DefR.SubReg) { in visitPHI()
631 const LatticeCell &T = Cells.get(DefR.Reg); in visitPHI()
633 Cells.update(DefR.Reg, Bottom); in visitPHI()
635 visitUsesOf(DefR.Reg); in visitPHI()
639 LatticeCell DefC = Cells.get(DefR.Reg); in visitPHI()
666 Cells.update(DefR.Reg, DefC); in visitPHI()
671 visitUsesOf(DefR.Reg); in visitPHI()
693 Register DefR(MO); in visitNonBranch() local
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| D | HexagonGenMux.cpp | 109 unsigned DefR, PredR; member
116 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
338 auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR) in genMuxInBlock()
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| D | HexagonConstExtenders.cpp | 1525 unsigned DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); in insertInitializer() local
1539 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::PS_fi), DefR) in insertInitializer()
1546 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_tfrsi), DefR) in insertInitializer()
1551 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR) in insertInitializer()
1556 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR) in insertInitializer()
1564 InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR) in insertInitializer()
1576 return { DefR, 0 }; in insertInitializer()
1893 Register DefR = insertInitializer(Q.first, P.first); in replaceExtenders() local
1894 NewRegs.push_back(DefR.Reg); in replaceExtenders()
1896 Changed |= replaceInstr(I, DefR, P.first); in replaceExtenders()
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| D | HexagonEarlyIfConv.cpp | 441 unsigned DefR = MI.getOperand(0).getReg(); in isValid() local
442 if (isPredicate(DefR)) in isValid()
995 unsigned DefR = PN->getOperand(0).getReg(); in eliminatePhis() local
1002 const TargetRegisterClass *RC = MRI->getRegClass(DefR); in eliminatePhis()
1007 MRI->replaceRegWith(DefR, NewR); in eliminatePhis()
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| D | HexagonBitSimplify.cpp | 1224 unsigned DefR = UseI.getOperand(0).getReg(); in computeUsedBits() local
1225 if (!TargetRegisterInfo::isVirtualRegister(DefR)) in computeUsedBits()
1227 Pending.push_back(DefR); in computeUsedBits()
2914 unsigned DefR; member
2921 bool isBitShuffle(const MachineInstr *MI, unsigned DefR) const;
2922 bool isStoreInput(const MachineInstr *MI, unsigned DefR) const;
2940 DefR = HexagonLoopRescheduling::getDefReg(&P); in PhiInfo()
2975 unsigned DefR) const { in isBitShuffle()
3129 dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi(" in processLoop()
3157 unsigned DefR = Defs.find_first(); in processLoop() local
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| D | HexagonOptAddrMode.cpp | 97 bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
725 unsigned DefR = MI->getOperand(0).getReg(); in processBlock() local
730 if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc)) in processBlock()
754 if (op.isReg() && op.isUse() && DefR == op.getReg()) in processBlock()
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| D | HexagonBitTracker.cpp | 957 if (unsigned DefR = getUniqueDefVReg(MI)) { in evaluate() local
958 if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) { in evaluate()
959 BT::RegisterRef PD(DefR, 0); in evaluate()
962 RegisterCell RC = RegisterCell::self(DefR, RW); in evaluate()
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| /external/llvm/lib/Target/Hexagon/ |
| D | RDFCopy.cpp | 59 RegisterRef DefR = { Dst.getReg(), Dst.getSubReg() }; in interpretAsCopy() local
65 unsigned S = DFG.getTRI().composeSubRegIndices(DefR.Sub, I.SubIdx); in interpretAsCopy()
66 RegisterRef DR = { DefR.Reg, S }; in interpretAsCopy()
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| D | HexagonGenMux.cpp | 73 unsigned DefR, PredR; member
79 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
299 BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR) in genMuxInBlock()
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| D | HexagonBitSimplify.cpp | 1167 unsigned DefR = UseI.getOperand(0).getReg(); in computeUsedBits() local
1168 if (!TargetRegisterInfo::isVirtualRegister(DefR)) in computeUsedBits()
1170 Pending.push_back(DefR); in computeUsedBits()
2331 unsigned DefR; member
2338 bool isBitShuffle(const MachineInstr *MI, unsigned DefR) const;
2339 bool isStoreInput(const MachineInstr *MI, unsigned DefR) const;
2357 DefR = HexagonLoopRescheduling::getDefReg(&P); in PhiInfo()
2395 unsigned DefR) const { in isBitShuffle()
2553 dbgs() << ' ' << PrintReg(I.DefR, HRI) << "=phi(" in processLoop()
2581 unsigned DefR = Defs.find_first(); in processLoop() local
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| D | HexagonOptAddrMode.cpp | 80 bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
530 unsigned DefR = MI->getOperand(0).getReg(); in processBlock() local
535 if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc)) in processBlock()
558 if (op.isReg() && op.isUse() && DefR == op.getReg()) in processBlock()
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| D | HexagonEarlyIfConv.cpp | 418 unsigned DefR = MI.getOperand(0).getReg(); in isValid() local
419 const TargetRegisterClass *RC = MRI->getRegClass(DefR); in isValid()
957 unsigned DefR = PN->getOperand(0).getReg(); in eliminatePhis() local
964 const TargetRegisterClass *RC = MRI->getRegClass(DefR); in eliminatePhis()
969 MRI->replaceRegWith(DefR, NewR); in eliminatePhis()
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