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Searched refs:DefRC (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp290 const TargetRegisterClass *DefRC, in shareSameRegisterFile() argument
295 if (DefRC == SrcRC) in shareSameRegisterFile()
301 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
309 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
314 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
317 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
320 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
325 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
DDetectDeadLanes.cpp376 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes() local
390 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) { in determineInitialDefinedLanes()
DPeepholeOptimizer.cpp624 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource() local
685 ShouldRewrite = TRI->shouldRewriteCopySrc(DefRC, SubReg, SrcRC, in findNextSource()
938 const TargetRegisterClass *DefRC = MRI.getRegClass(Def.Reg); in RewriteSource() local
939 unsigned NewVR = MRI.createVirtualRegister(DefRC); in RewriteSource()
DRegisterCoalescer.cpp930 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); in reMaterializeTrivialDef() local
942 if (!DefRC->contains(NewDstReg)) in reMaterializeTrivialDef()
973 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef()
1021 if (DefRC != nullptr) { in reMaterializeTrivialDef()
1023 NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx); in reMaterializeTrivialDef()
1025 NewRC = TRI->getCommonSubClass(NewRC, DefRC); in reMaterializeTrivialDef()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp351 const TargetRegisterClass *DefRC, in shareSameRegisterFile() argument
356 if (DefRC == SrcRC) in shareSameRegisterFile()
362 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
370 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
375 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
378 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
381 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
386 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
DDetectDeadLanes.cpp374 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes() local
388 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) { in determineInitialDefinedLanes()
DPeepholeOptimizer.cpp669 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource() local
732 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC, in findNextSource()
1232 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource() local
1233 unsigned NewVReg = MRI->createVirtualRegister(DefRC); in rewriteSource()
DRegisterCoalescer.cpp1146 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); in reMaterializeTrivialDef() local
1158 if (!DefRC->contains(NewDstReg)) in reMaterializeTrivialDef()
1189 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef()
1238 if (DefRC != nullptr) { in reMaterializeTrivialDef()
1240 NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx); in reMaterializeTrivialDef()
1242 NewRC = TRI->getCommonSubClass(NewRC, DefRC); in reMaterializeTrivialDef()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelDAGToDAG.cpp156 const TargetRegisterClass *DefRC = in FixRegisterClasses() local
164 if (!DefRC || !UseRC) in FixRegisterClasses()
167 if ((isCC(DefRC) && !isDCC(UseRC)) || (isCC(UseRC) && !isDCC(DefRC))) { in FixRegisterClasses()
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h135 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
DSIRegisterInfo.cpp808 const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
828 return getCommonSubClass(DefRC, SrcRC) != nullptr; in shouldRewriteCopySrc()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp723 const TargetRegisterClass *DefRC = nullptr; in select() local
725 DefRC = TRI.getRegClass(DefReg); in select()
730 DefRC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>(); in select()
731 if (!DefRC) { in select()
737 DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI); in select()
738 if (!DefRC) { in select()
746 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h167 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
DSIRegisterInfo.cpp1355 const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
1375 return getCommonSubClass(DefRC, SrcRC) != nullptr; in shouldRewriteCopySrc()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h517 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h552 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86SpeculativeLoadHardening.cpp2062 auto *DefRC = MRI->getRegClass(OldDefReg); in hardenPostLoad() local
2067 unsigned UnhardenedReg = MRI->createVirtualRegister(DefRC); in hardenPostLoad()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonConstPropagation.cpp1942 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg); in evaluate() local
1943 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo); in evaluate()
1944 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate()