/external/llvm/lib/Target/AArch64/ |
D | AArch64RedundantCopyElimination.cpp | 126 unsigned DefReg = MI->getOperand(0).getReg(); in optimizeCopy() local 130 !MRI->isReserved(DefReg) && in optimizeCopy() 131 (TargetReg == DefReg || TRI->isSuperRegister(DefReg, TargetReg))) { in optimizeCopy() 140 TRI->isSubRegister(SmallestDef, DefReg) ? DefReg : SmallestDef; in optimizeCopy()
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/external/llvm/lib/CodeGen/ |
D | DetectDeadLanes.cpp | 256 unsigned DefReg = Def.getReg(); in transferUsedLanes() local 257 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes() 291 unsigned DefReg = Def.getReg(); in transferDefinedLanesStep() local 292 if (!TargetRegisterInfo::isVirtualRegister(DefReg)) in transferDefinedLanesStep() 294 unsigned DefRegIdx = TargetRegisterInfo::virtReg2Index(DefReg); in transferDefinedLanesStep() 434 unsigned DefReg = Def.getReg(); in determineInitialUsedLanes() local 437 if (TargetRegisterInfo::isVirtualRegister(DefReg)) { in determineInitialUsedLanes() 441 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() 476 unsigned DefReg = Def.getReg(); in isUndefInput() local 477 if (!TargetRegisterInfo::isVirtualRegister(DefReg)) in isUndefInput() [all …]
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D | TailDuplicator.cpp | 308 unsigned DefReg = MI->getOperand(0).getReg(); in processPHI() local 313 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in processPHI() 314 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg))); in processPHI() 320 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) in processPHI() 321 addSSAUpdateEntry(DefReg, NewDef, PredBB); in processPHI()
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D | ImplicitNullChecks.cpp | 495 unsigned DefReg = NoRegister; in insertFaultingLoad() local 497 DefReg = LoadMI->defs().begin()->getReg(); in insertFaultingLoad() 502 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_LOAD_OP), DefReg) in insertFaultingLoad()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
D | DetectDeadLanes.cpp | 254 unsigned DefReg = Def.getReg(); in transferUsedLanes() local 255 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes() 289 unsigned DefReg = Def.getReg(); in transferDefinedLanesStep() local 290 if (!TargetRegisterInfo::isVirtualRegister(DefReg)) in transferDefinedLanesStep() 292 unsigned DefRegIdx = TargetRegisterInfo::virtReg2Index(DefReg); in transferDefinedLanesStep() 432 unsigned DefReg = Def.getReg(); in determineInitialUsedLanes() local 435 if (TargetRegisterInfo::isVirtualRegister(DefReg)) { in determineInitialUsedLanes() 439 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() 474 unsigned DefReg = Def.getReg(); in isUndefInput() local 475 if (!TargetRegisterInfo::isVirtualRegister(DefReg)) in isUndefInput() [all …]
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D | TailDuplicator.cpp | 344 unsigned DefReg = MI->getOperand(0).getReg(); in processPHI() local 349 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in processPHI() 350 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg))); in processPHI() 356 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) in processPHI() 357 addSSAUpdateEntry(DefReg, NewDef, PredBB); in processPHI()
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D | ImplicitNullChecks.cpp | 621 unsigned DefReg = NoRegister; in insertFaultingInstr() local 623 DefReg = MI->getOperand(0).getReg(); in insertFaultingInstr() 634 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg) in insertFaultingInstr()
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D | MachineSink.cpp | 1026 for (auto DefReg : DefedRegsInCopy) { in getSingleLiveInSuccBB() local 1028 getSingleLiveInSuccBB(CurBB, SinkableBBs, DefReg, TRI); in getSingleLiveInSuccBB() 1059 for (auto DefReg : DefedRegsInCopy) in updateLiveIn() local 1060 SuccBB->removeLiveIn(DefReg); in updateLiveIn()
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D | LiveVariables.cpp | 218 unsigned DefReg = MO.getReg(); in FindLastPartialDef() local 219 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef() 220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true); in FindLastPartialDef()
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/external/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyRegStackify.cpp | 392 unsigned DefReg = MO.getReg(); in OneUseDominatesOtherUses() local 393 if (!TargetRegisterInfo::isVirtualRegister(DefReg) || in OneUseDominatesOtherUses() 394 !MFI.isVRegStackified(DefReg)) in OneUseDominatesOtherUses() 396 assert(MRI.hasOneUse(DefReg)); in OneUseDominatesOtherUses() 397 const MachineOperand &NewUse = *MRI.use_begin(DefReg); in OneUseDominatesOtherUses() 549 unsigned DefReg = MRI.createVirtualRegister(RegClass); in MoveAndTeeForMultiUse() local 554 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in MoveAndTeeForMultiUse() 556 DefMO.setReg(DefReg); in MoveAndTeeForMultiUse() 570 LIS.createAndComputeVirtRegInterval(DefReg); in MoveAndTeeForMultiUse() 571 MFI.stackifyVReg(DefReg); in MoveAndTeeForMultiUse()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64InstructionSelector.cpp | 720 const unsigned DefReg = I.getOperand(0).getReg(); in select() local 721 const LLT DefTy = MRI.getType(DefReg); in select() 724 if (TargetRegisterInfo::isPhysicalRegister(DefReg)) { in select() 725 DefRC = TRI.getRegClass(DefReg); in select() 728 MRI.getRegClassOrRegBank(DefReg); in select() 746 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select() 807 const unsigned DefReg = I.getOperand(0).getReg(); in select() local 808 const LLT DefTy = MRI.getType(DefReg); in select() 810 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select() 866 .addDef(DefReg) in select() [all …]
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D | AArch64RedundantCopyElimination.cpp | 383 MCPhysReg DefReg = MI->getOperand(0).getReg(); in optimizeBlock() local 386 if (!MRI->isReserved(DefReg) && in optimizeBlock() 390 if (KnownReg.Reg != DefReg && in optimizeBlock() 391 !TRI->isSuperRegister(DefReg, KnownReg.Reg)) in optimizeBlock()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyRegStackify.cpp | 425 unsigned DefReg = MO.getReg(); in OneUseDominatesOtherUses() local 426 if (!TargetRegisterInfo::isVirtualRegister(DefReg) || in OneUseDominatesOtherUses() 427 !MFI.isVRegStackified(DefReg)) in OneUseDominatesOtherUses() 429 assert(MRI.hasOneUse(DefReg)); in OneUseDominatesOtherUses() 430 const MachineOperand &NewUse = *MRI.use_begin(DefReg); in OneUseDominatesOtherUses() 584 unsigned DefReg = MRI.createVirtualRegister(RegClass); in MoveAndTeeForMultiUse() local 589 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in MoveAndTeeForMultiUse() 591 DefMO.setReg(DefReg); in MoveAndTeeForMultiUse() 605 LIS.createAndComputeVirtRegInterval(DefReg); in MoveAndTeeForMultiUse() 606 MFI.stackifyVReg(DefReg); in MoveAndTeeForMultiUse()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86InstructionSelector.cpp | 500 const unsigned DefReg = I.getOperand(0).getReg(); in selectLoadStoreOp() local 501 LLT Ty = MRI.getType(DefReg); in selectLoadStoreOp() 502 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp() 526 addFullAddress(MIB, AM).addUse(DefReg); in selectLoadStoreOp() 548 const unsigned DefReg = I.getOperand(0).getReg(); in selectFrameIndexOrGep() local 549 LLT Ty = MRI.getType(DefReg); in selectFrameIndexOrGep() 601 const unsigned DefReg = I.getOperand(0).getReg(); in selectGlobalValue() local 602 LLT Ty = MRI.getType(DefReg); in selectGlobalValue() 620 const unsigned DefReg = I.getOperand(0).getReg(); in selectConstant() local 621 LLT Ty = MRI.getType(DefReg); in selectConstant() [all …]
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D | X86DomainReassignment.cpp | 602 unsigned DefReg = DefOp.getReg(); in buildClosure() local 603 if (!TargetRegisterInfo::isVirtualRegister(DefReg)) { in buildClosure() 607 visitRegister(C, DefReg, Domain, Worklist); in buildClosure()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | TargetInstrInfoImpl.cpp | 368 unsigned DefReg = MI->getOperand(0).getReg(); in isReallyTriviallyReMaterializableGeneric() local 374 if (TargetRegisterInfo::isVirtualRegister(DefReg) && in isReallyTriviallyReMaterializableGeneric() 375 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg)) in isReallyTriviallyReMaterializableGeneric() 439 if (MO.isDef() && Reg != DefReg) in isReallyTriviallyReMaterializableGeneric()
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D | TailDuplication.cpp | 382 unsigned DefReg = MI->getOperand(0).getReg(); in ProcessPHI() local 386 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in ProcessPHI() 387 LocalVRMap.insert(std::make_pair(DefReg, SrcReg)); in ProcessPHI() 393 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) in ProcessPHI() 394 AddSSAUpdateEntry(DefReg, NewDef, PredBB); in ProcessPHI()
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D | LiveVariables.cpp | 214 unsigned DefReg = MO.getReg(); in FindLastPartialDef() local 215 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef() 216 PartDefRegs.insert(DefReg); in FindLastPartialDef() 217 for (const unsigned *SubRegs = TRI->getSubRegisters(DefReg); in FindLastPartialDef()
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D | PHIElimination.cpp | 135 unsigned DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction() local 136 if (MRI->use_nodbg_empty(DefReg)) in runOnMachineFunction()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCVSXSwapRemoval.cpp | 665 unsigned DefReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local 671 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs() 695 unsigned DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs() local 714 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs() 753 unsigned DefReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local 755 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
D | PPCVSXSwapRemoval.cpp | 674 unsigned DefReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local 680 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs() 704 unsigned DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs() local 723 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs() 763 unsigned DefReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local 765 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
D | Mips16InstrInfo.cpp | 374 int DefReg = 0; in loadImmediate() local 378 DefReg = MO.getReg(); in loadImmediate() 397 if (DefReg != Reg) { in loadImmediate() 412 if (DefReg!= SpReg) { in loadImmediate()
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/external/llvm/lib/Target/Mips/ |
D | Mips16InstrInfo.cpp | 354 int DefReg = 0; in loadImmediate() local 358 DefReg = MO.getReg(); in loadImmediate() 377 if (DefReg != Reg) { in loadImmediate() 392 if (DefReg!= SpReg) { in loadImmediate()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
D | FastISel.cpp | 204 unsigned DefReg = findSinkableLocalRegDef(LocalMI); in flushLocalValueMap() local 205 if (DefReg == 0) in flushLocalValueMap() 208 sinkLocalValueMaterialization(LocalMI, DefReg, OrderMap); in flushLocalValueMap() 219 static bool isRegUsedByPhiNodes(unsigned DefReg, in isRegUsedByPhiNodes() argument 222 if (P.second == DefReg) in isRegUsedByPhiNodes() 248 unsigned DefReg, in sinkLocalValueMaterialization() argument 255 if (FuncInfo.RegsWithFixups.count(DefReg)) in sinkLocalValueMaterialization() 260 bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo); in sinkLocalValueMaterialization() 261 if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) { in sinkLocalValueMaterialization() 279 for (MachineInstr &UseInst : MRI.use_nodbg_instructions(DefReg)) { in sinkLocalValueMaterialization() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
D | BPFISelDAGToDAG.cpp | 96 bool checkLoadDef(unsigned DefReg, unsigned match_load_op); 639 bool BPFDAGToDAGISel::checkLoadDef(unsigned DefReg, unsigned match_load_op) { in checkLoadDef() argument 640 auto it = load_to_vreg_.find(DefReg); in checkLoadDef()
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