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/external/lzma/CPP/7zip/Archive/7z/
D7zItem.h95 CBoolVector Defs; member
100 Defs.ClearAndSetSize(newSize); in ClearAndSetSize()
106 Defs.Clear(); in Clear()
112 Defs.ReserveDown(); in ReserveDown()
118 if (index < Defs.Size() && Defs[index]) in GetItem()
127 bool ValidAndDefined(unsigned i) const { return i < Defs.Size() && Defs[i]; } in ValidAndDefined()
129 bool CheckSize(unsigned size) const { return Defs.Size() == size || Defs.Size() == 0; } in CheckSize()
137 CBoolVector Defs; member
142 Defs.Clear(); in Clear()
148 Defs.ReserveDown(); in ReserveDown()
[all …]
D7zOut.cpp337 const unsigned numDefined = BoolVector_CountSum(digests.Defs); in WriteHashDigests()
342 if (numDefined == digests.Defs.Size()) in WriteHashDigests()
347 WriteBoolVector(digests.Defs); in WriteHashDigests()
350 for (unsigned i = 0; i < digests.Defs.Size(); i++) in WriteHashDigests()
351 if (digests.Defs[i]) in WriteHashDigests()
445 digests2.Defs.Add(digests.Defs[digestIndex]); in WriteSubStreamsInfo()
495 const unsigned numDefined = BoolVector_CountSum(v.Defs); in WriteUInt64DefVector()
499 WriteAlignedBools(v.Defs, numDefined, type, 3); in WriteUInt64DefVector()
501 for (unsigned i = 0; i < v.Defs.Size(); i++) in WriteUInt64DefVector()
502 if (v.Defs[i]) in WriteUInt64DefVector()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZInstrSystem.td26 let hasSideEffects = 1, Defs = [CC] in {
32 let Uses = [R2L], Defs = [R2L] in
120 let hasSideEffects = 1, Defs = [CC] in
124 let hasSideEffects = 1, Defs = [CC] in
140 let hasSideEffects = 1, mayStore = 1, Uses = [R0D], Defs = [R0D, CC] in
144 let mayLoad = 1, mayStore = 1, Defs = [CC] in {
162 let Predicates = [FeatureEnhancedDAT2], hasSideEffects = 1, Defs = [CC] in
170 let hasSideEffects = 1, Defs = [CC] in {
176 let hasSideEffects = 1, Defs = [CC] in
180 let hasSideEffects = 1, Defs = [CC] in {
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DSystemZInstrHFP.td22 let Defs = [CC] in {
61 let Defs = [CC] in {
72 let Defs = [CC] in {
78 let Defs = [CC] in {
89 let Defs = [CC] in {
96 let Defs = [CC] in {
103 let Defs = [CC] in {
132 let Defs = [CC] in {
143 let Defs = [CC] in {
153 let Defs = [CC] in {
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DSystemZInstrDFP.td23 let Defs = [CC] in {
61 let Defs = [CC] in {
73 let Defs = [CC] in {
111 let Defs = [CC, R1L, F0Q], Uses = [R0L, F4Q] in
138 let Defs = [CC] in {
150 let Defs = [CC] in {
201 let Defs = [CC] in {
207 let Defs = [CC] in {
213 let Defs = [CC] in {
219 let Defs = [CC] in {
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/external/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp67 BitVector Defs, Uses; member
68 DefUseInfo() : Defs(), Uses() {} in DefUseInfo()
69 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {} in DefUseInfo()
91 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
122 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, in getDefsUses() argument
129 expandReg(*R++, Defs); in getDefsUses()
139 BitVector &Set = Mo->isDef() ? Defs : Uses; in getDefsUses()
149 BitVector Defs(NR), Uses(NR); in buildMaps() local
154 Defs.reset(); in buildMaps()
156 getDefsUses(MI, Defs, Uses); in buildMaps()
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DHexagonInstrInfoV3.td33 let Defs = !if (CSR, VolatileV3.Regs, []);
52 let Defs = !if (CSR, VolatileV3.Regs, []);
69 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs in
72 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [PC, R31, R6, R7, P0] in
85 let isCodeGenOnly = 1, Defs = VolatileV3.Regs in {
97 let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23 in
198 let Defs = [USR_OVF], hasSideEffects = 0 in
227 let Defs = [USR_OVF], hasSideEffects = 0 in
270 let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23 in
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DThumb2ITBlockPass.cpp45 SmallSet<unsigned, 4> &Defs,
56 SmallSet<unsigned, 4> &Defs, in TrackDefUses() argument
85 Defs.insert(Reg); in TrackDefUses()
88 Defs.insert(*Subreg); in TrackDefUses()
109 SmallSet<unsigned, 4> &Defs, in MoveCopyOutOfITBlock() argument
124 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
166 SmallSet<unsigned, 4> Defs; in InsertITInstructions() local
179 Defs.clear(); in InsertITInstructions()
181 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
218 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIFormMemoryClauses.cpp67 bool canBundle(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
69 void collectRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
70 bool processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses,
199 RegUse &Defs, RegUse &Uses) const { in canBundle() argument
216 RegUse &Map = MO.isDef() ? Uses : Defs; in canBundle()
255 RegUse &Defs, RegUse &Uses) const { in collectRegUses() argument
266 RegUse &Map = MO.isDef() ? Defs : Uses; in collectRegUses()
283 RegUse &Defs, RegUse &Uses, in processRegUses() argument
285 if (!canBundle(MI, Defs, Uses)) in processRegUses()
291 collectRegUses(MI, Defs, Uses); in processRegUses()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp101 BitVector Defs, Uses; member
104 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {} in DefUseInfo()
130 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
159 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, in getDefsUses() argument
166 expandReg(*R++, Defs); in getDefsUses()
176 BitVector &Set = MO.isDef() ? Defs : Uses; in getDefsUses()
185 BitVector Defs(NR), Uses(NR); in buildMaps() local
190 Defs.reset(); in buildMaps()
192 getDefsUses(MI, Defs, Uses); in buildMaps()
193 DUM.insert(std::make_pair(Index, DefUseInfo(Defs, Uses))); in buildMaps()
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DHexagonPseudo.td82 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
86 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
92 Defs = [PC, LC0], Uses = [SA0, LC0] in {
99 Defs = [PC, LC1], Uses = [SA1, LC1] in {
106 Defs = [PC, LC0, LC1], Uses = [SA0, SA1, LC0, LC1] in {
150 let Defs = [SA0, LC0, USR], isCodeGenOnly = 1, isExtended = 1,
157 let Defs = [SA1, LC1], isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
178 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [R16],
183 Defs = [PC, R31, R6, R7, P0] in
219 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
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/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td91 class Defs<list<Register> Regs> {
92 list<Register> Defs = Regs;
547 Defs<[DSPOutFlag20]>;
551 IsCommutable, Defs<[DSPOutFlag20]>;
555 Defs<[DSPOutFlag20]>;
559 Defs<[DSPOutFlag20]>;
563 Defs<[DSPOutFlag20]>;
567 IsCommutable, Defs<[DSPOutFlag20]>;
571 Defs<[DSPOutFlag20]>;
575 Defs<[DSPOutFlag20]>;
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DMipsDelaySlotFiller.cpp118 BitVector Defs, Uses; member in __anonbcf044610111::RegDefsUses
182 SmallPtrSet<ValueType, 4> Uses, Defs; member in __anonbcf044610111::MemDefsUses
320 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {} in RegDefsUses()
329 Defs.set(Mips::RA); in init()
335 Defs.reset(Mips::AT); in init()
346 Defs.set(Mips::RA); in setCallerSaved()
347 Defs.set(Mips::RA_64); in setCallerSaved()
361 Defs |= CallerSavedRegs; in setCallerSaved()
374 Defs |= AllocSet.flip(); in setUnallocatableRegs()
397 Defs |= NewDefs; in update()
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DMicroMipsDSPInstrInfo.td190 "absq_s.ph", int_mips_absq_s_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
192 "absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>;
194 "absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
228 Defs<[DSPOutFlag22]>;
231 Defs<[DSPOutFlag22]>;
234 Defs<[DSPOutFlag22]>;
237 Defs<[DSPOutFlag22]>;
262 "shllv.ph", int_mips_shll_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
265 Defs<[DSPOutFlag22]>;
267 "shllv.qb", int_mips_shll_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td92 class Defs<list<Register> Regs> {
93 list<Register> Defs = Regs;
552 Defs<[DSPOutFlag20]>;
556 IsCommutable, Defs<[DSPOutFlag20]>;
560 Defs<[DSPOutFlag20]>;
564 Defs<[DSPOutFlag20]>;
568 Defs<[DSPOutFlag20]>;
572 IsCommutable, Defs<[DSPOutFlag20]>;
576 Defs<[DSPOutFlag20]>;
580 Defs<[DSPOutFlag20]>;
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DMipsDelaySlotFiller.cpp138 BitVector Defs, Uses; member in __anon615354b90111::RegDefsUses
204 SmallPtrSet<ValueType, 4> Uses, Defs; member in __anon615354b90111::MemDefsUses
348 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {} in RegDefsUses()
357 Defs.set(Mips::RA); in init()
363 Defs.reset(Mips::AT); in init()
374 Defs.set(Mips::RA); in setCallerSaved()
375 Defs.set(Mips::RA_64); in setCallerSaved()
389 Defs |= CallerSavedRegs; in setCallerSaved()
402 Defs |= AllocSet.flip(); in setUnallocatableRegs()
425 Defs |= NewDefs; in update()
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/external/llvm/lib/Target/PowerPC/
DPPCBoolRetToInt.cpp62 SmallPtrSet<Value *, 8> Defs; in findAllDefs() local
65 Defs.insert(V); in findAllDefs()
71 if (Defs.insert(Op).second) in findAllDefs()
74 return Defs; in findAllDefs()
196 auto Defs = findAllDefs(U); in runOnUse() local
199 if (!std::any_of(Defs.begin(), Defs.end(), isa<Instruction, Value *>)) in runOnUse()
205 for (Value *V : Defs) in runOnUse()
209 for (Value *V : Defs) in runOnUse()
220 for (Value *V : Defs) in runOnUse()
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCChecker.cpp39 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0? in init()
40 Defs[Hexagon::LC0].insert(Unconditional); in init()
43 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0? in init()
44 Defs[Hexagon::LC1].insert(Unconditional); in init()
112 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
156 CurDefs.insert(*SRI), Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
169 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
334 if (!Defs.count(P) || LatePreds.count(P)) { in checkPredicates()
348 if (LatePreds.count(P) > 1 || Defs.count(P)) { in checkPredicates()
383 for (const auto& I : Defs) { in checkRegisters()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DThumb2ITBlockPass.cpp66 SmallSet<unsigned, 4> &Defs,
79 SmallSet<unsigned, 4> &Defs, in TrackDefUses() argument
109 Defs.insert(*Subreg); in TrackDefUses()
143 SmallSet<unsigned, 4> &Defs, in MoveCopyOutOfITBlock() argument
158 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
200 SmallSet<unsigned, 4> Defs; in InsertITInstructions() local
213 Defs.clear(); in InsertITInstructions()
215 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
256 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions()
266 TrackDefUses(NMI, Defs, Uses, TRI); in InsertITInstructions()
/external/llvm/lib/Target/ARM/
DThumb2ITBlockPass.cpp51 SmallSet<unsigned, 4> &Defs,
62 SmallSet<unsigned, 4> &Defs, in TrackDefUses() argument
92 Defs.insert(*Subreg); in TrackDefUses()
126 SmallSet<unsigned, 4> &Defs, in MoveCopyOutOfITBlock() argument
141 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
183 SmallSet<unsigned, 4> Defs; in InsertITInstructions() local
196 Defs.clear(); in InsertITInstructions()
198 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
239 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions()
249 TrackDefUses(NMI, Defs, Uses, TRI); in InsertITInstructions()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCBoolRetToInt.cpp74 SmallPtrSet<Value *, 8> Defs; in findAllDefs() local
77 Defs.insert(V); in findAllDefs()
86 if (Defs.insert(Op).second) in findAllDefs()
89 return Defs; in findAllDefs()
221 auto Defs = findAllDefs(U); in runOnUse() local
224 if (llvm::none_of(Defs, isa<Instruction, Value *>)) in runOnUse()
230 for (Value *V : Defs) in runOnUse()
235 for (Value *V : Defs) in runOnUse()
246 for (Value *V : Defs) in runOnUse()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DLiveVariables.cpp444 SmallVectorImpl<unsigned> &Defs) { in HandlePhysRegDef() argument
483 Defs.push_back(Reg); // Remember this def. in HandlePhysRegDef()
487 SmallVectorImpl<unsigned> &Defs) { in UpdatePhysRegDefs() argument
488 while (!Defs.empty()) { in UpdatePhysRegDefs()
489 unsigned Reg = Defs.back(); in UpdatePhysRegDefs()
490 Defs.pop_back(); in UpdatePhysRegDefs()
501 SmallVectorImpl<unsigned> &Defs) { in runOnInstr() argument
561 HandlePhysRegDef(MOReg, &MI, Defs); in runOnInstr()
563 UpdatePhysRegDefs(MI, Defs); in runOnInstr()
568 SmallVector<unsigned, 4> Defs; in runOnBlock() local
[all …]
/external/llvm/lib/CodeGen/
DLiveVariables.cpp444 SmallVectorImpl<unsigned> &Defs) { in HandlePhysRegDef() argument
483 Defs.push_back(Reg); // Remember this def. in HandlePhysRegDef()
487 SmallVectorImpl<unsigned> &Defs) { in UpdatePhysRegDefs() argument
488 while (!Defs.empty()) { in UpdatePhysRegDefs()
489 unsigned Reg = Defs.back(); in UpdatePhysRegDefs()
490 Defs.pop_back(); in UpdatePhysRegDefs()
501 SmallVectorImpl<unsigned> &Defs) { in runOnInstr() argument
561 HandlePhysRegDef(MOReg, &MI, Defs); in runOnInstr()
563 UpdatePhysRegDefs(MI, Defs); in runOnInstr()
568 SmallVector<unsigned, 4> Defs; in runOnBlock() local
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCChecker.cpp46 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0? in init()
47 Defs[Hexagon::LC0].insert(Unconditional); in init()
50 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0? in init()
51 Defs[Hexagon::LC1].insert(Unconditional); in init()
126 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
178 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
386 if (!Defs.count(P) || LatePreds.count(P)) { in checkPredicates()
399 if (LatePreds.count(P) > 1 || Defs.count(P)) { in checkPredicates()
498 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly() local
499 for (unsigned j = 0; j < Defs; ++j) { in checkRegistersReadOnly()
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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrControl.td15 let Defs = [ARGUMENTS] in {
32 } // Defs = [ARGUMENTS]
39 let Defs = [ARGUMENTS] in {
64 let Uses = [EXPR_STACK], Defs = [EXPR_STACK] in {
69 } // Uses = [EXPR_STACK], Defs = [EXPR_STACK]
95 } // Defs = [ARGUMENTS]

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