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Searched refs:DestSub1 (Results 1 – 3 of 3) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp2729 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitUnaryOp() local
2730 BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitUnaryOp()
2737 .addReg(DestSub1) in splitScalar64BitUnaryOp()
2793 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitBinaryOp() local
2794 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp()
2802 .addReg(DestSub1) in splitScalar64BitBinaryOp()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp4208 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitUnaryOp() local
4209 BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp()
4215 .addReg(DestSub1) in splitScalar64BitUnaryOp()
4236 unsigned DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitAddSub() local
4272 BuildMI(MBB, MII, DL, get(HiOpc), DestSub1) in splitScalar64BitAddSub()
4281 .addReg(DestSub1) in splitScalar64BitAddSub()
4339 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitBinaryOp() local
4340 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp()
4348 .addReg(DestSub1) in splitScalar64BitBinaryOp()
DSIISelLowering.cpp3257 unsigned DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in EmitInstrWithCustomInserter() local
3280 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1) in EmitInstrWithCustomInserter()
3286 .addReg(DestSub1) in EmitInstrWithCustomInserter()