Searched refs:DivUp (Results 1 – 2 of 2) sorted by relevance
| /external/tensorflow/tensorflow/core/util/ |
| D | cuda_launch_config.h | 108 inline int DivUp(int a, int b) { return (a + b - 1) / b; } in DivUp() function
135 std::min(DivUp(physical_thread_count, thread_per_block), in GetCudaLaunchConfig()
164 std::min(block_count, DivUp(work_element_count, thread_per_block)); in GetCudaLaunchConfig()
188 DivUp(work_element_count, fixed_block_size)); in GetCudaLaunchConfigFixedBlockSize()
223 int grid_x = std::min(DivUp(xdim, block_cols), max_blocks); in GetCuda2DLaunchConfig()
270 int blocksx = std::min({block_count, DivUp(xdim, threadsx), xgridlimit}); in GetCuda3DLaunchConfig()
272 {DivUp(block_count, blocksx), DivUp(ydim, threadsy), ygridlimit}); in GetCuda3DLaunchConfig()
273 int blocksz = std::min({DivUp(block_count, (blocksx * blocksy)), in GetCuda3DLaunchConfig()
274 DivUp(zdim, threadsz), zgridlimit}); in GetCuda3DLaunchConfig()
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| /external/tensorflow/tensorflow/core/kernels/ |
| D | depthwise_conv_op_gpu.h | 612 args.batch * DivUp(args.out_depth, kBlockDepth) * kBlockDepth; in LaunchDepthwiseConv2dGPUSmall()
621 DivUp(args.batch * args.out_depth, kBlockDepth) * kBlockDepth; in LaunchDepthwiseConv2dGPUSmall()
1607 args.batch * DivUp(args.out_depth, kBlockDepth) * kBlockDepth;
1615 DivUp(args.batch * args.out_depth, kBlockDepth) * kBlockDepth;
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