| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXCopy.cpp | 98 MachineOperand &DstMO = MI->getOperand(0); in processBlock() local
101 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
126 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
132 IsVRReg(DstMO.getReg(), MRI) ? &PPC::VSHRCRegClass : in processBlock()
134 assert((IsF8Reg(DstMO.getReg(), MRI) || in processBlock()
135 IsVSFReg(DstMO.getReg(), MRI) || in processBlock()
136 IsVSSReg(DstMO.getReg(), MRI) || in processBlock()
137 IsVRReg(DstMO.getReg(), MRI)) && in processBlock()
148 SrcMO.setSubReg(IsVRReg(DstMO.getReg(), MRI) ? PPC::sub_128 : in processBlock()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXCopy.cpp | 96 MachineOperand &DstMO = MI.getOperand(0); in processBlock() local
99 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
120 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
126 assert((IsF8Reg(DstMO.getReg(), MRI) || in processBlock()
127 IsVSFReg(DstMO.getReg(), MRI) || in processBlock()
128 IsVSSReg(DstMO.getReg(), MRI)) && in processBlock()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | ExpandPostRAPseudos.cpp | 153 MachineOperand &DstMO = MI->getOperand(0); in LowerCopy() local
156 if (SrcMO.getReg() == DstMO.getReg()) { in LowerCopy()
160 if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) { in LowerCopy()
174 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill()); in LowerCopy()
176 if (DstMO.isDead()) in LowerCopy()
177 TransferDeadFlag(MI, DstMO.getReg(), TRI); in LowerCopy()
|
| D | TwoAddressInstructionPass.cpp | 1144 const MachineOperand &DstMO = mi->getOperand(DstIdx); in runOnMachineFunction() local
1145 unsigned regA = DstMO.getReg(); in runOnMachineFunction()
1146 IsEarlyClobber |= DstMO.isEarlyClobber(); in runOnMachineFunction()
|
| /external/llvm/lib/CodeGen/ |
| D | ExpandPostRAPseudos.cpp | 146 MachineOperand &DstMO = MI->getOperand(0); in LowerCopy() local
149 if (SrcMO.getReg() == DstMO.getReg()) { in LowerCopy()
167 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill()); in LowerCopy()
|
| D | TwoAddressInstructionPass.cpp | 1414 MachineOperand &DstMO = MI->getOperand(DstIdx); in collectTiedOperands() local
1416 unsigned DstReg = DstMO.getReg(); in collectTiedOperands()
1424 if (SrcMO.isUndef() && !DstMO.getSubReg()) { in collectTiedOperands()
1448 const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second); in processTiedPairs() local
1449 IsEarlyClobber |= DstMO.isEarlyClobber(); in processTiedPairs()
1462 const MachineOperand &DstMO = MI->getOperand(DstIdx); in processTiedPairs() local
1463 unsigned RegA = DstMO.getReg(); in processTiedPairs()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | ExpandPostRAPseudos.cpp | 142 MachineOperand &DstMO = MI->getOperand(0); in LowerCopy() local
145 bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg()); in LowerCopy()
165 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill()); in LowerCopy()
|
| D | TwoAddressInstructionPass.cpp | 1469 MachineOperand &DstMO = MI->getOperand(DstIdx); in collectTiedOperands() local
1471 unsigned DstReg = DstMO.getReg(); in collectTiedOperands()
1479 if (SrcMO.isUndef() && !DstMO.getSubReg()) { in collectTiedOperands()
1503 const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second); in processTiedPairs() local
1504 IsEarlyClobber |= DstMO.isEarlyClobber(); in processTiedPairs()
1517 const MachineOperand &DstMO = MI->getOperand(DstIdx); in processTiedPairs() local
1518 unsigned RegA = DstMO.getReg(); in processTiedPairs()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 838 MachineOperand &DstMO = MIB->getOperand(SExtIdx); in mergePairedInsns() local
841 unsigned DstRegX = DstMO.getReg(); in mergePairedInsns()
845 DstMO.setReg(DstRegW); in mergePairedInsns()
|
| D | AArch64InstrInfo.cpp | 3073 const MachineOperand &DstMO = MI.getOperand(0); in foldMemoryOperandImpl() local
3075 unsigned DstReg = DstMO.getReg(); in foldMemoryOperandImpl()
3085 if (DstMO.getSubReg() == 0 && SrcMO.getSubReg() == 0) { in foldMemoryOperandImpl()
3107 if (IsSpill && DstMO.isUndef() && in foldMemoryOperandImpl()
3113 switch (DstMO.getSubReg()) { in foldMemoryOperandImpl()
3155 if (IsFill && SrcMO.getSubReg() == 0 && DstMO.isUndef()) { in foldMemoryOperandImpl()
3157 switch (DstMO.getSubReg()) { in foldMemoryOperandImpl()
3180 LoadDst.setSubReg(DstMO.getSubReg()); in foldMemoryOperandImpl()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 887 MachineOperand &DstMO = MIB->getOperand(SExtIdx); in mergePairedInsns() local
890 unsigned DstRegX = DstMO.getReg(); in mergePairedInsns()
894 DstMO.setReg(DstRegW); in mergePairedInsns()
|