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Searched refs:DstRC (Results 1 – 25 of 78) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp143 const TargetRegisterClass *DstRC = in getCopyRegClasses() local
148 return std::make_pair(SrcRC, DstRC); in getCopyRegClasses()
152 const TargetRegisterClass *DstRC, in isVGPRToSGPRCopy() argument
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
158 const TargetRegisterClass *DstRC, in isSGPRToVGPRCopy() argument
160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()
193 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
196 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
204 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
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DSILowerI1Copies.cpp102 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); in runOnMachineFunction() local
105 if (DstRC == &AMDGPU::VReg_1RegClass && in runOnMachineFunction()
132 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) && in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp175 const TargetRegisterClass *DstRC = in getCopyRegClasses() local
180 return std::make_pair(SrcRC, DstRC); in getCopyRegClasses()
184 const TargetRegisterClass *DstRC, in isVGPRToSGPRCopy() argument
186 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
190 const TargetRegisterClass *DstRC, in isSGPRToVGPRCopy() argument
192 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()
254 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
255 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
257 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
268 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
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DSILowerI1Copies.cpp102 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); in runOnMachineFunction() local
107 if (DstRC == &AMDGPU::VReg_1RegClass && in runOnMachineFunction()
135 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) && in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp109 const TargetRegisterClass *DstRC,
249 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy() local
251 if (SrcRC != DstRC) { in selectCopy()
253 unsigned ExtSrc = MRI.createVirtualRegister(DstRC); in selectCopy()
277 const TargetRegisterClass *DstRC = in selectCopy() local
287 if (DstRC != SrcRC) { in selectCopy()
288 I.getOperand(1).setSubReg(getSubRegIndex(DstRC)); in selectCopy()
297 if (!OldRC || !DstRC->hasSubClassEq(OldRC)) { in selectCopy()
298 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
664 static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC, in canTurnIntoCOPY() argument
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DX86InstrMMX.td128 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
131 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
132 [(set DstRC:$dst, (Int SrcRC:$src))], d>,
134 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
135 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>,
140 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
142 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
143 (ins DstRC:$src1, SrcRC:$src2), asm,
144 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>,
146 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
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/external/llvm/lib/CodeGen/
DDetectDeadLanes.cpp157 const TargetRegisterClass *DstRC, in isCrossCopy() argument
162 if (DstRC == SrcRC) in isCrossCopy()
187 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
190 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
192 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
193 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
441 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() local
442 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); in determineInitialUsedLanes()
490 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput() local
491 *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO); in isUndefInput()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DDetectDeadLanes.cpp155 const TargetRegisterClass *DstRC, in isCrossCopy() argument
160 if (DstRC == SrcRC) in isCrossCopy()
185 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
188 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
190 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
191 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
439 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() local
440 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); in determineInitialUsedLanes()
488 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput() local
489 *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO); in isUndefInput()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrMMX.td104 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
107 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
108 [(set DstRC:$dst, (Int SrcRC:$src))], d>;
109 def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
110 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
114 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
116 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst),(ins DstRC:$src1, SrcRC:$src2),
117 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
118 def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
119 (ins DstRC:$src1, x86memop:$src2), asm,
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp137 const TargetRegisterClass *SrcRC = 0, *DstRC = 0; in EmitCopyFromReg() local
142 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
145 DstRC = UseRC; in EmitCopyFromReg()
147 DstRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
156 VRBase = MRI->createVirtualRegister(DstRC); in EmitCopyFromReg()
294 const TargetRegisterClass *DstRC = 0; in AddRegisterOperand() local
296 DstRC = TII->getRegClass(*II, IIOpNum, TRI); in AddRegisterOperand()
297 assert((DstRC || (MCID.isVariadic() && IIOpNum >= MCID.getNumOperands())) && in AddRegisterOperand()
299 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { in AddRegisterOperand()
300 unsigned NewVReg = MRI->createVirtualRegister(DstRC); in AddRegisterOperand()
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/external/llvm/utils/TableGen/
DFastISelEmitter.cpp193 const CodeGenRegisterClass *DstRC = nullptr; in initialize() local
275 if (DstRC) { in initialize()
276 if (DstRC != RC && !DstRC->hasSubClass(RC)) in initialize()
279 DstRC = RC; in initialize()
479 const CodeGenRegisterClass *DstRC = nullptr; in collectPatterns() local
487 DstRC = &Target.getRegisterClass(Op0Rec); in collectPatterns()
488 if (!DstRC) in collectPatterns()
527 DstRC)) in collectPatterns()
578 DstRC, in collectPatterns()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp157 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local
162 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
165 DstRC = UseRC; in EmitCopyFromReg()
167 DstRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
176 VRBase = MRI->createVirtualRegister(DstRC); in EmitCopyFromReg()
333 const TargetRegisterClass *DstRC = nullptr; in AddRegisterOperand() local
335 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); in AddRegisterOperand()
336 assert((!DstRC || TargetRegisterInfo::isVirtualRegister(VReg)) && in AddRegisterOperand()
338 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { in AddRegisterOperand()
339 unsigned NewVReg = MRI->createVirtualRegister(DstRC); in AddRegisterOperand()
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/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DFastISelEmitter.cpp204 const CodeGenRegisterClass *DstRC = nullptr; in initialize() local
282 if (DstRC) { in initialize()
283 if (DstRC != RC && !DstRC->hasSubClass(RC)) in initialize()
286 DstRC = RC; in initialize()
489 const CodeGenRegisterClass *DstRC = nullptr; in collectPatterns() local
497 DstRC = &Target.getRegisterClass(Op0Rec); in collectPatterns()
498 if (!DstRC) in collectPatterns()
537 DstRC)) in collectPatterns()
587 DstRC, in collectPatterns()
/external/llvm/lib/Target/X86/
DX86InstrMMX.td185 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
188 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
189 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr, d>,
191 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
192 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm, d>,
197 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
199 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
200 (ins DstRC:$src1, SrcRC:$src2), asm,
201 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
203 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
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/external/swiftshader/third_party/LLVM/utils/TableGen/
DFastISelEmitter.cpp186 const CodeGenRegisterClass *DstRC = 0; in initialize() local
266 if (DstRC) { in initialize()
267 if (DstRC != RC && !DstRC->hasSubClass(RC)) in initialize()
270 DstRC = RC; in initialize()
455 const CodeGenRegisterClass *DstRC = 0; in collectPatterns() local
463 DstRC = &Target.getRegisterClass(Op0Rec); in collectPatterns()
464 if (!DstRC) in collectPatterns()
542 DstRC, in collectPatterns()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsInstrFormats.td273 RegisterClass DstRC, RegisterClass SrcRC> :
274 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
281 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> :
282 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
284 [(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp125 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass; in processBlock() local
132 unsigned NewVReg = MRI.createVirtualRegister(DstRC); in processBlock()
/external/llvm/lib/Target/Mips/
DMipsInstrFPU.td121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
144 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
146 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
147 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT;
149 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
151 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
152 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT;
154 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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DMicroMips32r6InstrInfo.td668 class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
671 dag OutOperandList = (outs DstRC:$rs);
678 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
682 dag OutOperandList = (outs DstRC:$fs);
684 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
690 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
692 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
693 dag OutOperandList = (outs DstRC:$fs);
703 class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
706 dag OutOperandList = (outs DstRC:$impl);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMicroMips32r6InstrInfo.td654 class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
657 dag OutOperandList = (outs DstRC:$rs);
665 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
669 dag OutOperandList = (outs DstRC:$fs);
671 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
677 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
679 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
680 dag OutOperandList = (outs DstRC:$fs);
690 class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
693 dag OutOperandList = (outs DstRC:$impl);
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DMipsInstrFPU.td126 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
128 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
129 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
149 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
151 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
152 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {
156 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
158 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
159 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT {
163 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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/external/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp131 const TargetRegisterClass *DstRC = in processBlock() local
141 unsigned NewVReg = MRI.createVirtualRegister(DstRC); in processBlock()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DInstructionSelect.cpp172 auto DstRC = MRI.getRegClass(DstReg); in runOnMachineFunction() local
173 if (SrcRC == DstRC) { in runOnMachineFunction()
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXInstrInfo.cpp72 const TargetRegisterClass *DstRC, in copyRegToReg() argument
75 if (DstRC != SrcRC) in copyRegToReg()
79 if (DstRC == map[i].cls) { in copyRegToReg()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegisterCoalescer.cpp157 const TargetRegisterClass *DstRC,
290 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters() local
291 if (!TRI.getCommonSubClass(DstRC, SrcRC)) in setRegisters()
307 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters() local
309 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
311 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
314 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1104 const TargetRegisterClass *DstRC, in isWinToJoinCrossClass() argument
1140 if (DstRC != NewRC && DstSize > ThresSize) { in isWinToJoinCrossClass()
1141 unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC); in isWinToJoinCrossClass()

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