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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrArithmetic.td48 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
54 (implicit EFLAGS)]>; // AL,AH = AL*GR8
56 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
61 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
64 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/]>;
65 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
68 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/]>;
70 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
77 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
80 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
[all …]
DX86InstrCMovSetCC.td18 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
24 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>,TB,OpSize;
29 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))]>, TB;
34 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>, TB;
37 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst" in {
42 CondNode, EFLAGS))]>, TB, OpSize;
47 CondNode, EFLAGS))]>, TB;
52 CondNode, EFLAGS))]>, TB;
53 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
78 let Uses = [EFLAGS] in {
[all …]
DX86InstrCompiler.td44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
88 let Defs = [EFLAGS] in
95 (implicit EFLAGS)]>;
105 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
115 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP, EAX] in
122 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP, RAX] in
159 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
[all …]
DX86InstrInfo.td33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
736 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
739 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
768 let Defs = [EFLAGS] in {
771 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
774 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
778 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
781 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
784 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
[all …]
DX86InstrControl.td51 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
55 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
144 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
183 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
219 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
250 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
267 // __chkstk(MSVC): clobber R10, R11 and EFLAGS.
268 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
269 let Defs = [RAX, R10, R11, RSP, EFLAGS],
283 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td60 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
66 (implicit EFLAGS)], IIC_MUL8>, Sched<[WriteIMul]>;
68 let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
73 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in
76 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/],
79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
82 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
85 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
92 (implicit EFLAGS)], IIC_MUL8>, SchedLoadReg<WriteIMulLd>;
95 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
[all …]
DX86InstrCMovSetCC.td18 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
24 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))],
30 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
36 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))],
40 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
46 CondNode, EFLAGS))], IIC_CMOV16_RM>,
52 CondNode, EFLAGS))], IIC_CMOV32_RM>,
58 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
59 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
84 let Uses = [EFLAGS] in {
[all …]
DX86InstrCompiler.td44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
63 // sub / add which can clobber EFLAGS.
64 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
79 let usesCustomInserter = 1, Defs = [EFLAGS] in {
89 (implicit EFLAGS)]>;
93 let Defs = [EFLAGS] in
100 (implicit EFLAGS)]>;
108 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
115 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
[all …]
DX86InstrInfo.td33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
1155 let Defs = [ESP, EFLAGS], Uses = [ESP] in
1160 let Defs = [RSP, EFLAGS], Uses = [RSP] in
1166 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1174 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1213 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1216 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1248 let Defs = [EFLAGS] in {
1251 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrArithmetic.td60 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
66 (implicit EFLAGS)]>, Sched<[WriteIMul]>;
68 let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
73 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in
76 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/]>,
79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
82 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/]>,
85 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
92 (implicit EFLAGS)]>, SchedLoadReg<WriteIMul.Folded>;
95 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
[all …]
DX86InstrCMovSetCC.td19 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
25 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>,
31 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))]>,
37 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>, TB;
40 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
46 CondNode, EFLAGS))]>, TB, OpSize16;
51 CondNode, EFLAGS))]>, TB, OpSize32;
56 CondNode, EFLAGS))]>, TB;
57 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
82 let Uses = [EFLAGS] in {
[all …]
DX86InstrCompiler.td49 // sub / add which can clobber EFLAGS.
50 let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in {
67 // sub / add which can clobber EFLAGS.
68 let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in {
83 let usesCustomInserter = 1, Defs = [EFLAGS] in {
93 (implicit EFLAGS)]>;
97 let Defs = [EFLAGS] in
104 (implicit EFLAGS)]>;
112 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
119 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
[all …]
DX86InstrInfo.td33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
1270 let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in
1275 let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in
1281 let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1288 let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0,
1333 let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1336 let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in
1373 let Defs = [EFLAGS] in {
1376 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>,
[all …]
DX86FlagsCopyLowering.cpp370 MI.getOperand(0).getReg() == X86::EFLAGS) in runOnMachineFunction()
413 assert(DOp.getReg() == X86::EFLAGS && "Unexpected copy def register!"); in runOnMachineFunction()
441 return &MI != CopyI && MI.findRegisterDefOperand(X86::EFLAGS); in runOnMachineFunction()
467 while (TestMBB->isLiveIn(X86::EFLAGS) && !TestMBB->pred_empty() && in runOnMachineFunction()
499 return MI.findRegisterDefOperand(X86::EFLAGS); in runOnMachineFunction()
561 MachineOperand *FlagUse = MI.findRegisterUseOperand(X86::EFLAGS); in runOnMachineFunction()
563 if (MI.findRegisterDefOperand(X86::EFLAGS)) { in runOnMachineFunction()
612 assert(MI.findRegisterDefOperand(X86::EFLAGS) && in runOnMachineFunction()
655 if (SuccMBB->isLiveIn(X86::EFLAGS) && in runOnMachineFunction()
713 (MI.getOperand(0).getReg() == X86::EFLAGS || in runOnMachineFunction()
[all …]
DX86CmovConversion.cpp346 if (I.definesRegister(X86::EFLAGS)) { in collectCmovCandidates()
573 if (MI->killsRegister(X86::EFLAGS)) in checkEFLAGSLive()
583 if (I->readsRegister(X86::EFLAGS)) in checkEFLAGSLive()
585 if (I->definesRegister(X86::EFLAGS)) in checkEFLAGSLive()
591 if ((*I)->isLiveIn(X86::EFLAGS)) in checkEFLAGSLive()
685 FalseMBB->addLiveIn(X86::EFLAGS); in convertCmovInstsToBranches()
686 SinkMBB->addLiveIn(X86::EFLAGS); in convertCmovInstsToBranches()
DX86SpeculativeLoadHardening.cpp481 ZeroI->findRegisterDefOperand(X86::EFLAGS); in runOnMachineFunction()
726 bool LiveEFLAGS = Succ.isLiveIn(X86::EFLAGS); in tracePredStateThroughCFG()
728 CheckingMBB.addLiveIn(X86::EFLAGS); in tracePredStateThroughCFG()
754 CMovI->findRegisterUseOperand(X86::EFLAGS)->setIsKill(true); in tracePredStateThroughCFG()
1078 if (!MI.findRegisterDefOperand(X86::EFLAGS)->isDead()) { in isDataInvariant()
1247 if (!MI.findRegisterDefOperand(X86::EFLAGS)->isDead()) { in isDataInvariantLoad()
1323 if (MachineOperand *DefOp = MI.findRegisterDefOperand(X86::EFLAGS)) { in isEFLAGSLive()
1333 if (MI.killsRegister(X86::EFLAGS, &TRI)) in isEFLAGSLive()
1339 return MBB.isLiveIn(X86::EFLAGS); in isEFLAGSLive()
1621 BuildMI(MBB, InsertPt, Loc, TII->get(X86::COPY), Reg).addReg(X86::EFLAGS); in saveEFLAGS()
[all …]
/external/llvm/test/CodeGen/X86/
Dhandle-move.ll11 ; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def>, %EDX<imp-def,dead>, %EFLAGS<imp-def,dead>, %EAX<imp-u…
28 ; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def,dead>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-u…
61 ; Move EFLAGS dead def across another def:
62 ; handleMove 208B -> 36B: %EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
63 ; EFLAGS: [20r,20d:4)[160r,160d:3)[208r,208d:0)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0@208…
Dremat-phys-dead.ll12 ; CHECK: Remat: %EAX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %AL<imp-def>
21 ; CHECK: Remat: %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
Dpeephole-na-phys-copy-folding.ll8 ; EFLAGS. Make sure the flags are used directly, instead of needlessly using
127 ; cmpxchg sets EFLAGS, call clobbers it, then br uses EFLAGS.
158 ; Restore result of the first cmpxchg from D, put it back in EFLAGS.
164 ; Test from EFLAGS restored from first cmpxchg, jump if that fails.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dhandle-move.ll11 ; 144B -> 180B: DIV32r %4, implicit-def %eax, implicit dead %edx, implicit dead %EFLAGS, implicit k…
28 ; 144B -> 180B: DIV32r %4, implicit dead %eax, implicit-def %edx, implicit dead %EFLAGS, implicit k…
61 ; Move EFLAGS dead def across another def:
62 ; handleMove 208B -> 36B: %edx = MOV32r0 implicit dead %EFLAGS
63 ; EFLAGS: [20r,20d:4)[160r,160d:3)[208r,208d:0)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0@208…
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Duint64-to-float.ll28 ; %vreg7<def> = CMOV_FR32 %vreg6<kill>, %vreg5<kill>, 15, %EFLAGS<imp-use>; FR32:%vreg7,%vreg6,%v…
30 ; If the instruction had an EFLAGS<kill> flag, it wouldn't need to mark EFLAGS
/external/syzkaller/pkg/report/testdata/linux/report/
D14219 [ 95.884331] RSP: 0018:ffff8801db407e88 EFLAGS: 00010086
39 [ 95.884453] RSP: 0018:ffff8801ce13fac8 EFLAGS: 00000246 ORIG_RAX: ffffffffffffff07
68 [ 95.884720] RSP: 002b:00007f6b9af6ac58 EFLAGS: 00000212 ORIG_RAX: 0000000000000029
D446 [ 56.163554] RSP: 0018:ffff8801c5e37720 EFLAGS: 00010212
89 [ 56.359673] RSP: 002b:00007f7e59d4fc08 EFLAGS: 00000216 ORIG_RAX: 0000000000000010
118 RSP: 0018:ffff8801c5e37720 EFLAGS: 00010212
129 RSP: 002b:00007f7e59d4fc08 EFLAGS: 00000216 ORIG_RAX: 0000000000000010
D16018 [ 190.757101] RSP: 0018:ffff88021fd07d10 EFLAGS: 00010006
42 [ 190.757101] RSP: 0018:ffff8801aa906f20 EFLAGS: 00000297 ORIG_RAX: ffffffffffffff10
98 [ 190.757101] RSP: 002b:00007f80206dac88 EFLAGS: 00000246 ORIG_RAX: 00000000000000ca
D6713 [ 562.797675] RSP: 0018:ffff8801bf6676f0 EFLAGS: 00000246 ORIG_RAX: ffffffffffffff11
70 [ 563.077845] RSP: 002b:00000000f7ec61fc EFLAGS: 00000246 ORIG_RAX: 0000000000000004
113 [ 563.300525] RSP: 0018:ffff8801bf6676f0 EFLAGS: 00000246 ORIG_RAX: ffffffffffffff11
164 [ 563.542980] RSP: 002b:00000000f7ec61fc EFLAGS: 00000246 ORIG_RAX: 0000000000000004

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