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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2010
4  * Texas Instruments, <www.ti.com>
5  *
6  * Authors:
7  *	Aneesh V <aneesh@ti.com>
8  *	Sricharan R <r.sricharan@ti.com>
9  */
10 
11 #ifndef _OMAP5_H_
12 #define _OMAP5_H_
13 
14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
15 #include <asm/types.h>
16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
17 
18 #include <linux/sizes.h>
19 
20 /*
21  * L4 Peripherals - L4 Wakeup and L4 Core now
22  */
23 #define OMAP54XX_L4_CORE_BASE	0x4A000000
24 #define OMAP54XX_L4_WKUP_BASE	0x4Ae00000
25 #define OMAP54XX_L4_PER_BASE	0x48000000
26 
27 /* CONTROL ID CODE */
28 #define CONTROL_CORE_ID_CODE	0x4A002204
29 #define CONTROL_WKUP_ID_CODE	0x4AE0C204
30 
31 #if defined(CONFIG_DRA7XX)
32 #define CONTROL_ID_CODE		CONTROL_WKUP_ID_CODE
33 #else
34 #define CONTROL_ID_CODE		CONTROL_CORE_ID_CODE
35 #endif
36 
37 #if defined(CONFIG_DRA7XX)
38 #define DRA7_USB_OTG_SS1_BASE		0x48890000
39 #define DRA7_USB_OTG_SS1_GLUE_BASE	0x48880000
40 #define DRA7_USB3_PHY1_PLL_CTRL		0x4A084C00
41 #define DRA7_USB3_PHY1_POWER		0x4A002370
42 #define DRA7_USB2_PHY1_POWER		0x4A002300
43 
44 #define DRA7_USB_OTG_SS2_BASE		0x488D0000
45 #define DRA7_USB_OTG_SS2_GLUE_BASE	0x488C0000
46 #define DRA7_USB2_PHY2_POWER		0x4A002E74
47 #else
48 #define OMAP5XX_USB_OTG_SS_BASE		0x4A030000
49 #define OMAP5XX_USB_OTG_SS_GLUE_BASE	0x4A020000
50 #define OMAP5XX_USB3_PHY_PLL_CTRL	0x4A084C00
51 #define OMAP5XX_USB3_PHY_POWER		0x4A002370
52 #define OMAP5XX_USB2_PHY_POWER		0x4A002300
53 #endif
54 
55 /* To be verified */
56 #define OMAP5430_CONTROL_ID_CODE_ES1_0		0x0B94202F
57 #define OMAP5430_CONTROL_ID_CODE_ES2_0          0x1B94202F
58 #define OMAP5432_CONTROL_ID_CODE_ES1_0		0x0B99802F
59 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
60 #define DRA762_CONTROL_ID_CODE_ES1_0		0x0BB5002F
61 #define DRA752_CONTROL_ID_CODE_ES1_0		0x0B99002F
62 #define DRA752_CONTROL_ID_CODE_ES1_1		0x1B99002F
63 #define DRA752_CONTROL_ID_CODE_ES2_0		0x2B99002F
64 #define DRA722_CONTROL_ID_CODE_ES1_0		0x0B9BC02F
65 #define DRA722_CONTROL_ID_CODE_ES2_0		0x1B9BC02F
66 #define DRA722_CONTROL_ID_CODE_ES2_1		0x2B9BC02F
67 
68 #define DRA762_ABZ_PACKAGE			0x2
69 #define DRA762_ACD_PACKAGE			0x3
70 
71 /* UART */
72 #define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
73 #define UART2_BASE		(OMAP54XX_L4_PER_BASE + 0x6c000)
74 #define UART3_BASE		(OMAP54XX_L4_PER_BASE + 0x20000)
75 #define UART4_BASE		(OMAP54XX_L4_PER_BASE + 0x6e000)
76 
77 /* General Purpose Timers */
78 #define GPT1_BASE		(OMAP54XX_L4_WKUP_BASE + 0x18000)
79 #define GPT2_BASE		(OMAP54XX_L4_PER_BASE  + 0x32000)
80 #define GPT3_BASE		(OMAP54XX_L4_PER_BASE  + 0x34000)
81 
82 /* Watchdog Timer2 - MPU watchdog */
83 #define WDT2_BASE		(OMAP54XX_L4_WKUP_BASE + 0x14000)
84 
85 /* QSPI */
86 #define QSPI_BASE		0x4B300000
87 
88 /* SATA */
89 #define DWC_AHSATA_BASE		0x4A140000
90 
91 /*
92  * Hardware Register Details
93  */
94 
95 /* Watchdog Timer */
96 #define WD_UNLOCK1		0xAAAA
97 #define WD_UNLOCK2		0x5555
98 
99 /* GP Timer */
100 #define TCLR_ST			(0x1 << 0)
101 #define TCLR_AR			(0x1 << 1)
102 #define TCLR_PRE		(0x1 << 5)
103 
104 /* Control Module */
105 #define LDOSRAM_ACTMODE_VSET_IN_MASK	(0x1F << 5)
106 #define LDOSRAM_VOLT_CTRL_OVERRIDE	0x0401040f
107 #define CONTROL_EFUSE_1_OVERRIDE	0x1C4D0110
108 #define CONTROL_EFUSE_2_OVERRIDE	0x00084000
109 
110 /* LPDDR2 IO regs */
111 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
112 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
113 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN	0x7C7C7C7C
114 #define LPDDR2IO_GR10_WD_MASK				(3 << 17)
115 #define CONTROL_LPDDR2IO_3_VAL		0xA0888C00
116 
117 /* CONTROL_EFUSE_2 */
118 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
119 
120 #define SDCARD_BIAS_PWRDNZ				(1 << 27)
121 #define SDCARD_PWRDNZ					(1 << 26)
122 #define SDCARD_BIAS_HIZ_MODE				(1 << 25)
123 #define SDCARD_PBIASLITE_VMODE				(1 << 21)
124 
125 #ifndef __ASSEMBLY__
126 
127 struct s32ktimer {
128 	unsigned char res[0x10];
129 	unsigned int s32k_cr;	/* 0x10 */
130 };
131 
132 #define DEVICE_TYPE_SHIFT 0x6
133 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
134 
135 /* Output impedance control */
136 #define ds_120_ohm	0x0
137 #define ds_60_ohm	0x1
138 #define ds_45_ohm	0x2
139 #define ds_30_ohm	0x3
140 #define ds_mask		0x3
141 
142 /* Slew rate control */
143 #define sc_slow		0x0
144 #define sc_medium	0x1
145 #define sc_fast		0x2
146 #define sc_na		0x3
147 #define sc_mask		0x3
148 
149 /* Target capacitance control */
150 #define lb_5_12_pf	0x0
151 #define lb_12_25_pf	0x1
152 #define lb_25_50_pf	0x2
153 #define lb_50_80_pf	0x3
154 #define lb_mask		0x3
155 
156 #define usb_i_mask	0x7
157 
158 #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN   0x80828082
159 #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
160 #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
161 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
162 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
163 
164 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL	0x7C7C7C6C
165 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL	0x64646464
166 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE				0xBAE8C631
167 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE				0xBC6318DC
168 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE				0x0
169 
170 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
171 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464
172 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
173 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC
174 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
175 
176 #define EFUSE_1 0x45145100
177 #define EFUSE_2 0x45145100
178 #define EFUSE_3 0x45145100
179 #define EFUSE_4 0x45145100
180 #endif /* __ASSEMBLY__ */
181 
182 /*
183  * In all cases, the TRM defines the RAM Memory Map for the processor
184  * and indicates the area for the downloaded image.  We use all of that
185  * space for download and once up and running may use other parts of the
186  * map for our needs.  We set a scratch space that is at the end of the
187  * OMAP5 download area, but within the DRA7xx download area (as it is
188  * much larger) and do not, at this time, make use of the additional
189  * space.
190  */
191 #if defined(CONFIG_DRA7XX)
192 #define NON_SECURE_SRAM_START	0x40300000
193 #define NON_SECURE_SRAM_END	0x40380000	/* Not inclusive */
194 #define NON_SECURE_SRAM_IMG_END	0x4037C000
195 #else
196 #define NON_SECURE_SRAM_START	0x40300000
197 #define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */
198 #define NON_SECURE_SRAM_IMG_END	0x4031E000
199 #endif
200 #define SRAM_SCRATCH_SPACE_ADDR	(NON_SECURE_SRAM_IMG_END - SZ_1K)
201 
202 /* base address for indirect vectors (internal boot mode) */
203 #define SRAM_ROM_VECT_BASE	0x4031F000
204 
205 /* CONTROL_SRCOMP_XXX_SIDE */
206 #define OVERRIDE_XS_SHIFT		30
207 #define OVERRIDE_XS_MASK		(1 << 30)
208 #define SRCODE_READ_XS_SHIFT		12
209 #define SRCODE_READ_XS_MASK		(0xff << 12)
210 #define PWRDWN_XS_SHIFT			11
211 #define PWRDWN_XS_MASK			(1 << 11)
212 #define DIVIDE_FACTOR_XS_SHIFT		4
213 #define DIVIDE_FACTOR_XS_MASK		(0x7f << 4)
214 #define MULTIPLY_FACTOR_XS_SHIFT	1
215 #define MULTIPLY_FACTOR_XS_MASK		(0x7 << 1)
216 #define SRCODE_OVERRIDE_SEL_XS_SHIFT	0
217 #define SRCODE_OVERRIDE_SEL_XS_MASK	(1 << 0)
218 
219 /* ABB settings */
220 #define OMAP_ABB_SETTLING_TIME		50
221 #define OMAP_ABB_CLOCK_CYCLES		16
222 
223 /* ABB tranxdone mask */
224 #define OMAP_ABB_MPU_TXDONE_MASK		(0x1 << 7)
225 #define OMAP_ABB_MM_TXDONE_MASK			(0x1 << 31)
226 #define OMAP_ABB_IVA_TXDONE_MASK		(0x1 << 30)
227 #define OMAP_ABB_EVE_TXDONE_MASK		(0x1 << 29)
228 #define OMAP_ABB_GPU_TXDONE_MASK		(0x1 << 28)
229 
230 /* ABB efuse masks */
231 #define OMAP5_PROD_ABB_FUSE_VSET_MASK		(0x1F << 20)
232 #define OMAP5_PROD_ABB_FUSE_ENABLE_MASK		(0x1 << 25)
233 #define DRA7_ABB_FUSE_VSET_MASK			(0x1F << 20)
234 #define DRA7_ABB_FUSE_ENABLE_MASK		(0x1 << 25)
235 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK	(0x1 << 10)
236 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK	(0x1f << 0)
237 
238 #ifndef __ASSEMBLY__
239 struct srcomp_params {
240 	s8 divide_factor;
241 	s8 multiply_factor;
242 };
243 
244 struct ctrl_ioregs {
245 	u32 ctrl_ddrch;
246 	u32 ctrl_lpddr2ch;
247 	u32 ctrl_ddr3ch;
248 	u32 ctrl_ddrio_0;
249 	u32 ctrl_ddrio_1;
250 	u32 ctrl_ddrio_2;
251 	u32 ctrl_emif_sdram_config_ext;
252 	u32 ctrl_emif_sdram_config_ext_final;
253 	u32 ctrl_ddr_ctrl_ext_0;
254 };
255 
256 void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits);
257 
258 #endif /* __ASSEMBLY__ */
259 
260 /* Boot parameters */
261 #ifndef __ASSEMBLY__
262 struct omap_boot_parameters {
263 	unsigned int boot_message;
264 	unsigned int boot_device_descriptor;
265 	unsigned char boot_device;
266 	unsigned char reset_reason;
267 	unsigned char ch_flags;
268 };
269 #endif
270 
271 #endif
272