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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2017 NXP
4  */
5 
6 #define ETH_1_1G_BUS_ID		0x1
7 #define ETH_1_1G_PHY_ID		0x1e
8 #define ETH_1_1G_MDIO_MUX	0x2
9 #define ETH_1G_MDIO_PHY_MASK	0xBFFFFFFD
10 #define ETH_1_1G_PHY_MODE	"sgmii"
11 #define ETH_2_1G_BUS_ID		0x1
12 #define ETH_2_1G_PHY_ID		0x1
13 #define ETH_2_1G_MDIO_MUX	0x1
14 #define ETH_2_1G_PHY_MODE	"rgmii"
15 
16 #define ETH_1_2_5G_BUS_ID	0x0
17 #define ETH_1_2_5G_PHY_ID	0x1
18 #define ETH_1_2_5G_MDIO_MUX	0x2
19 #define ETH_2_5G_MDIO_PHY_MASK	0xFFFFFFF9
20 #define ETH_2_5G_PHY_MODE	"sgmii-2500"
21 #define ETH_2_2_5G_BUS_ID	0x1
22 #define ETH_2_2_5G_PHY_ID	0x2
23 #define ETH_2_2_5G_MDIO_MUX	0x3
24 
25 #define SERDES_1_G_PROTOCOL	0x3508
26 #define SERDES_2_5_G_PROTOCOL	0x2205
27 
28 #define PFE_PROP_LEN		4
29 
30 #define ETH_1_PATH		"/pfe@04000000/ethernet@0"
31 #define ETH_1_MDIO		ETH_1_PATH "/mdio@0"
32 
33 #define ETH_2_PATH		"/pfe@04000000/ethernet@1"
34 #define ETH_2_MDIO		ETH_2_PATH "/mdio@0"
35 
36 #define NUM_ETH_NODE		2
37 
38 struct pfe_prop_val {
39 	int busid;
40 	int phyid;
41 	int mux_val;
42 	int phy_mask;
43 	char *phy_mode;
44 };
45