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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2009
4  * Graeme Russ, graeme.russ@gmail.com
5  *
6  * (C) Copyright 2002
7  * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
8  */
9 
10 #ifndef __ASM_INTERRUPT_H_
11 #define __ASM_INTERRUPT_H_ 1
12 
13 #include <asm/types.h>
14 
15 #define SYS_NUM_IRQS	16
16 
17 /* Architecture defined exceptions */
18 enum x86_exception {
19 	EXC_DE = 0,
20 	EXC_DB,
21 	EXC_NMI,
22 	EXC_BP,
23 	EXC_OF,
24 	EXC_BR,
25 	EXC_UD,
26 	EXC_NM,
27 	EXC_DF,
28 	EXC_CSO,
29 	EXC_TS,
30 	EXC_NP,
31 	EXC_SS,
32 	EXC_GP,
33 	EXC_PF,
34 	EXC_MF = 16,
35 	EXC_AC,
36 	EXC_MC,
37 	EXC_XM,
38 	EXC_VE
39 };
40 
41 /* arch/x86/cpu/interrupts.c */
42 void set_vector(u8 intnum, void *routine);
43 
44 /* Architecture specific functions */
45 void mask_irq(int irq);
46 void unmask_irq(int irq);
47 void specific_eoi(int irq);
48 
49 extern char exception_stack[];
50 
51 /**
52  * configure_irq_trigger() - Configure IRQ triggering
53  *
54  * Switch the given interrupt to be level / edge triggered
55  *
56  * @param int_num legacy interrupt number (3-7, 9-15)
57  * @param is_level_triggered true for level triggered interrupt, false for
58  *	edge triggered interrupt
59  */
60 void configure_irq_trigger(int int_num, bool is_level_triggered);
61 
62 void *x86_get_idt(void);
63 
64 #endif
65