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Searched refs:EXT5 (Results 1 – 4 of 4) sorted by relevance

/external/v8/src/ppc/
Ddisasm-ppc.cc278 if (opcode == EXT5 || in FormatOption()
292 if (instr->OpcodeValue() << 26 != EXT5) { in FormatOption()
300 if (instr->OpcodeValue() << 26 != EXT5) { in FormatOption()
1098 switch (EXT5 | (instr->BitField(4, 2))) { in DecodeExt5()
1116 switch (EXT5 | (instr->BitField(4, 1))) { in DecodeExt5()
1431 case EXT5: { in InstructionDecode()
Dassembler-ppc.cc377 return (((instr & kOpcodeMask) == EXT5) && in IsRldicl()
378 ((EXT5 | (instr & kExt5OpcodeMask)) == RLDICL)); in IsRldicl()
1143 md_form(EXT5 | RLDIC, ra, rs, sh, mb, r); in rldic()
1148 md_form(EXT5 | RLDICL, ra, rs, sh, mb, r); in rldicl()
1153 mds_form(EXT5 | RLDCL, ra, rs, rb, mb, r); in rldcl()
1158 md_form(EXT5 | RLDICR, ra, rs, sh, me, r); in rldicr()
1189 md_form(EXT5 | RLDIMI, ra, rs, sh, mb, r); in rldimi()
Dconstants-ppc.h2555 EXT5 = 0x78000000, // Extended code set 5 - 64bit only enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/GlobalISel/
Darm-param-lowering.ll211 ; CHECK: [[EXT5:%[0-9]+]]:_(s32) = G_EXTRACT [[RES_ARR]](s96), 64
215 ; CHECK: [[INS5:%[0-9]+]]:_(s96) = G_INSERT [[INS4]], [[EXT5]](s32), 64
356 ; CHECK: [[EXT5:%[0-9]+]]:_(s32) = G_EXTRACT [[R_MERGED]](s64), 32
359 ; CHECK: [[INS5:%[0-9]+]]:_(s64) = G_INSERT [[INS4]], [[EXT5]](s32), 32
400 ; CHECK: [[EXT5:%[0-9]+]]:_(s32) = G_EXTRACT [[Y_ARR]](s96), 32
412 ; CHECK: [[INS5:%[0-9]+]]:_(s96) = G_INSERT [[INS4]], [[EXT5]](s32), 32