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Searched refs:Enc (Results 1 – 25 of 33) sorted by relevance

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/external/swiftshader/third_party/subzero/pnacl-llvm/include/llvm/Bitcode/NaCl/
DNaClBitCodes.h123 explicit NaClBitCodeAbbrevOp(uint64_t V) : Enc(Literal), Val(V) {} in NaClBitCodeAbbrevOp()
126 Encoding getEncoding() const { return Enc; } in getEncoding()
128 static bool isValidEncoding(uint64_t Enc) { return Enc <= Encoding_MAX; } in isValidEncoding() argument
133 return hasValue(Enc); in hasValue()
139 bool isValid() const { return isValid(Enc, Val); } in isValid()
143 bool isLiteral() const { return Enc == Literal; } in isLiteral()
145 bool isArrayOp() const { return Enc == Array; } in isArrayOp()
196 int EncodingDiff = static_cast<int>(Enc) - static_cast<int>(Op.Enc); in Compare()
205 Encoding Enc; // The encoding to use.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/
DBPFRegisterInfo.td18 class Wi<bits<16> Enc, string n> : Register<n> {
19 let HWEncoding = Enc;
25 class Ri<bits<16> Enc, string n, list<Register> subregs>
27 let HWEncoding = Enc;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DSIMCCodeEmitter.cpp348 uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); in getSDWASrcEncoding() local
349 if (Enc != ~0U && Enc != 255) { in getSDWASrcEncoding()
350 return Enc | SDWA9EncValues::SRC_SGPR_MASK; in getSDWASrcEncoding()
431 uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); in getMachineOpValue() local
432 if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4)) in getMachineOpValue()
433 return Enc; in getMachineOpValue()
/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td30 class MipsReg<bits<16> Enc, string n> : Register<n> {
31 let HWEncoding = Enc;
35 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
37 let HWEncoding = Enc;
42 class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
45 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
46 : MipsRegWithSubRegs<Enc, n, subregs> {
51 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
54 class AFPR<bits<16> Enc, string n, list<Register> subregs>
55 : MipsRegWithSubRegs<Enc, n, subregs> {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsRegisterInfo.td30 class MipsReg<bits<16> Enc, string n> : Register<n> {
31 let HWEncoding = Enc;
35 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
37 let HWEncoding = Enc;
42 class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
45 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
46 : MipsRegWithSubRegs<Enc, n, subregs> {
51 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
54 class AFPR<bits<16> Enc, string n, list<Register> subregs>
55 : MipsRegWithSubRegs<Enc, n, subregs> {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td14 class SparcReg<bits<16> Enc, string n> : Register<n> {
15 let HWEncoding = Enc;
19 class SparcCtrlReg<bits<16> Enc, string n>: Register<n> {
20 let HWEncoding = Enc;
33 class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>;
36 class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
42 class Rf<bits<16> Enc, string n> : SparcReg<Enc, n>;
45 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
52 class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td14 class SparcReg<bits<16> Enc, string n> : Register<n> {
15 let HWEncoding = Enc;
19 class SparcCtrlReg<bits<16> Enc, string n>: Register<n> {
20 let HWEncoding = Enc;
33 class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>;
36 class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
42 class Rf<bits<16> Enc, string n> : SparcReg<Enc, n>;
45 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
52 class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Bitcode/
DBitCodes.h97 unsigned Enc : 3; // The encoding to use. variable
109 : Val(Data), IsLiteral(false), Enc(E) {} in Val()
118 Encoding getEncoding() const { assert(isEncoding()); return (Encoding)Enc; } in getEncoding()
/external/llvm/include/llvm/Bitcode/
DBitCodes.h90 unsigned Enc : 3; // The encoding to use. variable
102 : Val(Data), IsLiteral(false), Enc(E) {} in Val()
111 Encoding getEncoding() const { assert(isEncoding()); return (Encoding)Enc; } in getEncoding()
/external/swiftshader/third_party/LLVM/include/llvm/Bitcode/
DBitCodes.h87 unsigned Enc : 3; // The encoding to use. variable
99 : Val(Data), IsLiteral(false), Enc(E) {} in Val()
108 Encoding getEncoding() const { assert(isEncoding()); return (Encoding)Enc; } in getEncoding()
/external/swiftshader/third_party/subzero/pnacl-llvm/
DNaClBitCodes.cpp38 : Enc(E), Val(Data) { in NaClBitCodeAbbrevOp()
61 if (Enc == Literal) { in Print()
65 Stream << getEncodingName(Enc); in Print()
/external/clang/lib/CodeGen/
DTargetInfo.cpp7352 std::string Enc; member in __anoncb30615c1411::FieldEncoding
7354 FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {} in FieldEncoding()
7355 StringRef str() {return Enc.c_str();} in str()
7358 return Enc < rhs.Enc; in operator <()
7536 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
7542 SmallStringEnc Enc; in emitTargetMD() local
7543 if (getTypeString(Enc, D, CGM, TSC)) { in emitTargetMD()
7546 llvm::MDString::get(Ctx, Enc.str())}; in emitTargetMD()
7598 static bool appendType(SmallStringEnc &Enc, QualType QType,
7610 SmallStringEnc Enc; in extractFieldType() local
[all …]
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
DSIMCCodeEmitter.cpp286 uint32_t Enc = getLitEncoding(MO, RC.getSize()); in getMachineOpValue() local
287 if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4)) in getMachineOpValue()
288 return Enc; in getMachineOpValue()
/external/llvm/lib/Target/ARM/
DARMMCInstLower.cpp145 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm()); in LowerARMMachineInstrToMCInst() local
146 if (Enc != -1) in LowerARMMachineInstrToMCInst()
147 MCOp.setImm(Enc); in LowerARMMachineInstrToMCInst()
DARMRegisterInfo.td15 class ARMReg<bits<16> Enc, string n, list<Register> subregs = []> : Register<n> {
16 let HWEncoding = Enc;
23 class ARMFReg<bits<16> Enc, string n> : Register<n> {
24 let HWEncoding = Enc;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMMCInstLower.cpp160 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm()); in LowerARMMachineInstrToMCInst() local
161 if (Enc != -1) in LowerARMMachineInstrToMCInst()
162 MCOp.setImm(Enc); in LowerARMMachineInstrToMCInst()
DARMRegisterInfo.td17 class ARMReg<bits<16> Enc, string n, list<Register> subregs = []> : Register<n> {
18 let HWEncoding = Enc;
25 class ARMFReg<bits<16> Enc, string n> : Register<n> {
26 let HWEncoding = Enc;
/external/llvm/lib/Target/BPF/
DBPFRegisterInfo.td16 class Ri<bits<16> Enc, string n> : Register<n> {
18 let HWEncoding = Enc;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVRegisterInfo.td15 class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
16 let HWEncoding{4-0} = Enc;
20 class RISCVReg32<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
21 let HWEncoding{4-0} = Enc;
/external/honggfuzz/examples/apache-httpd/corpus_http1/
Db647c2d47e8461b753430bf0e6f19d73.000000a2.honggfuzz.cov3 Accept-Enc�Ĝ�f: idZ�0�˃����%��8�C|keep-`live�ty
/external/honggfuzz/examples/apache-httpd/corpus_http2/
Db647c2d47e8461b753430bf0e6f19d73.000000a2.honggfuzz.cov3 Accept-Enc�Ĝ�f: idZ�0�˃����%��8�C|keep-`live�ty
/external/ppp/pppd/plugins/radius/etc/
Ddictionary.microsoft13 ATTRIBUTE MS-CHAP-LM-Enc-PW 5 string Microsoft
14 ATTRIBUTE MS-CHAP-NT-Enc-PW 6 string Microsoft
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineModuleInfo.h246 void setCompactUnwindEncoding(uint32_t Enc) { CompactUnwindEncoding = Enc; } in setCompactUnwindEncoding() argument
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DX86FoldTablesEmitter.cpp479 uint64_t Enc = getValueFromBitsInit(RegRec->getValueAsBitsInit("OpEncBits")); in addEntryWithFlags() local
486 } else if (Enc != X86Local::XOP && Enc != X86Local::VEX && in addEntryWithFlags()
487 Enc != X86Local::EVEX) { in addEntryWithFlags()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInsertWaitcnts.cpp1221 unsigned Enc = AMDGPU::encodeWaitcnt(IV, in generateWaitcntInstBefore() local
1237 if (isWaitcntStronger(I->getOperand(0).getImm(), Enc)) in generateWaitcntInstBefore()
1241 Enc = combineWaitcnt(I->getOperand(0).getImm(), Enc); in generateWaitcntInstBefore()
1258 OldWaitcnt->getOperand(0).setImm(Enc); in generateWaitcntInstBefore()
1268 .addImm(Enc); in generateWaitcntInstBefore()

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