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Searched refs:EndGroup (Results 1 – 24 of 24) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZHazardRecognizer.cpp53 if (!SC->EndGroup) in getNumDecoderSlots()
192 if (SC->BeginGroup && SC->EndGroup) in dumpSU()
196 else if (SC->EndGroup) in dumpSU()
332 if (CurrGroupSize == GroupLim || SC->EndGroup) in EmitInstruction()
351 if (SC->EndGroup) { in groupingCost()
DSystemZScheduleZ196.td40 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
49 let EndGroup = 1;
90 let EndGroup = 1; }
111 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
112 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?J(G)?(Asm.*)?$")>;
113 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
114 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?B(R)?(Asm.*)?$")>;
131 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Cond)?Trap$")>;
149 def : InstRW<[WLat1, LSU, EndGroup], (instregex "Return$")>;
150 def : InstRW<[WLat1, LSU, EndGroup], (instregex "CondReturn$")>;
[all …]
DSystemZScheduleZEC12.td40 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
49 let EndGroup = 1;
93 let EndGroup = 1; }
119 def : InstRW<[WLat1, FXU, EndGroup], (instregex "BRCT(G)?$")>;
154 def : InstRW<[WLat1, LSU, EndGroup], (instregex "Return$")>;
559 def : InstRW<[WLat1, LSU, EndGroup], (instregex "Serialize$")>;
568 def : InstRW<[WLat1LSU, FXU, LSU, EndGroup], (instregex "TS$")>;
658 def : InstRW<[WLat3, FXU, EndGroup], (instregex "IPM$")>;
661 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
670 def : InstRW<[WLat1, LSU, EndGroup], (instregex "SAM(24|31|64)$")>;
[all …]
DSystemZSchedule.td19 def EndGroup : SchedWrite;
DSystemZScheduleZ13.td40 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
49 let EndGroup = 1;
105 let EndGroup = 1; }
131 def : InstRW<[WLat1, FXa, EndGroup], (instregex "BRCT(G)?$")>;
166 def : InstRW<[WLat1, FXb, EndGroup], (instregex "Return$")>;
577 def : InstRW<[FXb, EndGroup], (instregex "BPRP$")>;
584 def : InstRW<[WLat1, FXb, EndGroup], (instregex "Serialize$")>;
593 def : InstRW<[WLat2LSU, FXb, LSU, EndGroup], (instregex "TS$")>;
684 def : InstRW<[WLat3, FXa, EndGroup], (instregex "IPM$")>;
687 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
[all …]
DSystemZScheduleZ14.td40 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
49 let EndGroup = 1;
105 let EndGroup = 1; }
132 def : InstRW<[WLat1, FXa, EndGroup], (instregex "BRCT(G)?$")>;
167 def : InstRW<[WLat1, FXb, EndGroup], (instregex "Return$")>;
586 def : InstRW<[FXb, EndGroup], (instregex "BPRP$")>;
593 def : InstRW<[WLat1, FXb, EndGroup], (instregex "Serialize$")>;
602 def : InstRW<[WLat2LSU, FXb, LSU, EndGroup], (instregex "TS$")>;
703 def : InstRW<[WLat3, FXa, EndGroup], (instregex "IPM$")>;
706 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
[all …]
DSystemZMachineScheduler.cpp255 bool AffectsGrouping = (SC->isValid() && (SC->BeginGroup || SC->EndGroup)); in releaseTopNode()
/external/protobuf/csharp/src/Google.Protobuf.Test/
DCodedInputStreamTest.cs452 output.WriteTag(3, WireFormat.WireType.EndGroup); in SkipGroup()
455 output.WriteTag(2, WireFormat.WireType.EndGroup); in SkipGroup()
489 output.WriteTag(4, WireFormat.WireType.EndGroup); in SkipGroup_WrongEndGroupTag()
509 output.WriteTag(1, WireFormat.WireType.EndGroup); in RogueEndGroupTag()
514 Assert.AreEqual(WireFormat.MakeTag(1, WireFormat.WireType.EndGroup), input.ReadTag()); in RogueEndGroupTag()
525 output.WriteTag(2, WireFormat.WireType.EndGroup); in EndOfStreamReachedWhileSkippingGroup()
547 output.WriteTag(1, WireFormat.WireType.EndGroup); in RecursionLimitAppliedWhileSkippingGroup()
DGeneratedMessageTest.cs690 output.WriteTag(100, WireFormat.WireType.EndGroup); in ExtraEndGroupThrows()
/external/protobuf/csharp/src/Google.Protobuf/
DWireFormat.cs70 EndGroup = 4, enumerator
DCodedInputStream.cs407 case WireFormat.WireType.EndGroup: in SkipLastField()
444 if (WireFormat.GetTagWireType(tag) == WireFormat.WireType.EndGroup) in SkipGroup()
/external/llvm/include/llvm/MC/
DMCSchedule.h110 bool EndGroup; member
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCSchedule.h119 bool EndGroup : 1; member
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DSubtargetEmitter.cpp1004 SCDesc.EndGroup = false; in GenSchedClassTables()
1104 SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup"); in GenSchedClassTables()
1106 SCDesc.EndGroup |= WriteRes->getValueAsBit("SingleIssue"); in GenSchedClassTables()
1331 << ", " << ( MCDesc.EndGroup ? "true" : "false" ) in EmitSchedClassTables()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetSchedule.cpp103 return SC->EndGroup; in mustEndGroup()
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp816 SCDesc.EndGroup = false; in GenSchedClassTables()
924 SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup"); in GenSchedClassTables()
1134 << ", " << ( MCDesc.EndGroup ? "true" : "false" ) in EmitSchedClassTables()
/external/v8/src/inspector/
Dv8-console-message.cc50 return protocol::Runtime::ConsoleAPICalled::TypeEnum::EndGroup; in consoleAPITypeValue()
/external/llvm/include/llvm/Target/
DTargetSchedule.td254 bit EndGroup = 0;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTargetSchedule.td260 bit EndGroup = 0;
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc273 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
1293 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenSubtargetInfo.inc1514 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
2500 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
3486 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
4472 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
5458 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
6444 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
7430 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
8416 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
9402 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenSubtargetInfo.inc4710 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
5926 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
7142 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
8358 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
9574 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
10790 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
12006 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
13222 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
14438 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
/external/bcc/tests/cc/
Dcatch.hpp7571 virtual void EndGroup( std::string const& groupName, Totals const& totals ) = 0;
7669 m_legacyReporter->EndGroup( testGroupStats.groupInfo.name, testGroupStats.totals ); in testGroupEnded()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenSubtargetInfo.inc10539 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
11946 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
13353 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
14760 // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}