| /external/v8/src/wasm/baseline/arm64/ |
| D | liftoff-assembler-arm64.h | 405 I32_BINOP(i32_xor, Eor) in I32_BINOP()
414 I64_BINOP(i64_xor, Eor) in I32_BINOP()
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 1106 __ Eor(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction() local
1110 __ Eor(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction() local
1690 ATOMIC_BINOP_CASE(Xor, Eor) in AssembleArchInstruction()
2014 SIMD_BINOP_CASE(kArm64S128Xor, Eor, 16B); in AssembleArchInstruction()
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| /external/vixl/test/aarch32/ |
| D | test-disasm-a32.cc | 3335 COMPARE_T32(Eor(eq, r0, r0, r7), in TEST()
3339 COMPARE_T32(Eor(eq, r0, r0, 0x1), in TEST()
4043 CHECK_T32_16(Eor(DontCare, r7, r7, r6), "eors r7, r6\n"); in TEST()
4045 CHECK_T32_16_IT_BLOCK(Eor(DontCare, eq, r7, r7, r6), in TEST()
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 124 M(Eor) \
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| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 124 M(Eor) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 124 M(Eor) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 124 M(Eor) \
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| D | test-simulator-cond-rd-rn-operand-const-a32.cc | 124 M(Eor) \
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| D | test-simulator-cond-rd-rn-operand-const-t32.cc | 124 M(Eor) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 124 M(Eor) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 124 M(Eor) \
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| D | test-assembler-aarch32.cc | 3266 __ Eor(r0, r0, 0); in TEST() local
3310 __ Eor(r3, r0, 0xffffffff); in TEST() local
6050 CHECK_SIZE_MATCH(Eor(r7, r7, r6), Eor(r7, r6, r7)); in TEST_T32()
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| D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 124 M(Eor) \
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.h | 392 Eor, enumerator
1008 using InstARM32Eor = InstARM32ThreeAddrGPR<InstARM32::Eor>;
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| D | IceInstARM32.cpp | 3488 template class InstARM32ThreeAddrGPR<InstARM32::Eor>;
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 385 __ Eor(x11, x0, 0x18001); in TEST() local
837 __ Eor(w13, w0, kWMinInt); in TEST() local
1190 __ Eor(x2, x0, Operand(x1)); in TEST() local
1191 __ Eor(w3, w0, Operand(w1, LSL, 4)); in TEST() local
1192 __ Eor(x4, x0, Operand(x1, LSL, 4)); in TEST() local
1193 __ Eor(x5, x0, Operand(x1, LSR, 1)); in TEST() local
1194 __ Eor(w6, w0, Operand(w1, ASR, 20)); in TEST() local
1195 __ Eor(x7, x0, Operand(x1, ASR, 20)); in TEST() local
1196 __ Eor(w8, w0, Operand(w1, ROR, 28)); in TEST() local
1197 __ Eor(x9, x0, Operand(x1, ROR, 28)); in TEST() local
[all …]
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| D | test-disasm-aarch64.cc | 3357 COMPARE_MACRO(Eor(w4, w5, 0), "mov w4, w5"); in TEST()
3358 COMPARE_MACRO(Eor(x4, x5, 0), "mov x4, x5"); in TEST()
3373 COMPARE_MACRO(Eor(w16, w17, 0xffffffff), "mvn w16, w17"); in TEST()
3374 COMPARE_MACRO(Eor(x16, x17, 0xffffffff), "eor x16, x17, #0xffffffff"); in TEST()
3375 COMPARE_MACRO(Eor(x16, x17, 0xffffffffffffffff), "mvn x16, x17"); in TEST()
4921 COMPARE_MACRO(Eor(v6.V8B(), v7.V8B(), v8.V8B()), "eor v6.8b, v7.8b, v8.8b"); in TEST()
4922 COMPARE_MACRO(Eor(v6.V16B(), v7.V16B(), v8.V16B()), in TEST()
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| /external/v8/src/arm64/ |
| D | macro-assembler-arm64.h | 398 V(eor, Eor) \
619 inline void Eor(const Register& rd, const Register& rn,
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| D | macro-assembler-arm64-inl.h | 76 void TurboAssembler::Eor(const Register& rd, const Register& rn, in Eor() function
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 1691 void Eor(Condition cond, Register rd, Register rn, const Operand& operand) { in Eor() function
1715 void Eor(Register rd, Register rn, const Operand& operand) { in Eor() function
1716 Eor(al, rd, rn, operand); in Eor()
1718 void Eor(FlagsUpdate flags, in Eor() function
1725 Eor(cond, rd, rn, operand); in Eor()
1737 Eor(cond, rd, rn, operand); in Eor()
1742 void Eor(FlagsUpdate flags, in Eor() function
1746 Eor(flags, al, rd, rn, operand); in Eor()
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 657 void Eor(const Register& rd, const Register& rn, const Operand& operand);
2547 V(eor, Eor) \
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| D | macro-assembler-aarch64.cc | 784 void MacroAssembler::Eor(const Register& rd, in Eor() function in vixl::aarch64::MacroAssembler
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 44 # Vector And, Orr, Eor, Orn, Bic
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 44 # Vector And, Orr, Eor, Orn, Bic
|