| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonConstExtenders.cpp | 389 bool isRegOffOpcode(unsigned ExtOpc) const ;
390 unsigned getRegOffOpcode(unsigned ExtOpc) const;
391 unsigned getDirectRegReplacement(unsigned ExtOpc) const;
871 unsigned HCE::getRegOffOpcode(unsigned ExtOpc) const { in getRegOffOpcode()
875 switch (ExtOpc) { in getRegOffOpcode()
880 const MCInstrDesc &D = HII->get(ExtOpc); in getRegOffOpcode()
888 switch (ExtOpc) { in getRegOffOpcode()
961 if (!isStoreImmediate(ExtOpc)) in getRegOffOpcode()
962 return ExtOpc; in getRegOffOpcode()
971 unsigned HCE::getDirectRegReplacement(unsigned ExtOpc) const { in getDirectRegReplacement()
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| D | HexagonBitSimplify.cpp | 2502 unsigned ExtOpc = 0; in simplifyExtractLow() local
2505 ExtOpc = Signed ? Hexagon::A2_sxtb : Hexagon::A2_zxtb; in simplifyExtractLow()
2507 ExtOpc = Signed ? Hexagon::A2_sxth : Hexagon::A2_zxth; in simplifyExtractLow()
2509 ExtOpc = Hexagon::A2_andir; in simplifyExtractLow()
2511 if (ExtOpc == 0) { in simplifyExtractLow()
2512 ExtOpc = in simplifyExtractLow()
2524 if (!validateReg({R,SR}, ExtOpc, 1)) in simplifyExtractLow()
2528 if (MI->getOpcode() == ExtOpc) { in simplifyExtractLow()
2540 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR) in simplifyExtractLow()
2542 switch (ExtOpc) { in simplifyExtractLow()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 347 MachineInstrBuilder MachineIRBuilderBase::buildExtOrTrunc(unsigned ExtOpc, in buildExtOrTrunc() argument
350 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || in buildExtOrTrunc()
351 TargetOpcode::G_SEXT == ExtOpc) && in buildExtOrTrunc()
360 Opcode = ExtOpc; in buildExtOrTrunc()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 410 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, unsigned Res,
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1266 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND in LowerSETCC() local
1268 SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS); in LowerSETCC()
1269 SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS); in LowerSETCC()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 712 unsigned ExtOpc = in PromoteOperand() local
714 return DAG.getNode(ExtOpc, dl, PVT, Op); in PromoteOperand()
3869 unsigned ExtOpc, in ExtendUsesToFormExtLoad() argument
3883 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
3885 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1125 unsigned ExtOpc = in PromoteOperand() local
1127 return DAG.getNode(ExtOpc, DL, PVT, Op); in PromoteOperand()
7964 unsigned ExtOpc, in ExtendUsesToFormExtLoad() argument
7978 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
7980 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
8291 ISD::NodeType ExtOpc) { in tryToFoldExtOfLoad() argument
8302 DoXform = ExtendUsesToFormExtLoad(VT, N, N0, ExtOpc, SetCCs, TLI); in tryToFoldExtOfLoad()
8312 Combiner.ExtendSetCCUses(SetCCs, N0, ExtLoad, ExtOpc); in tryToFoldExtOfLoad()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 982 unsigned ExtOpc = in PromoteOperand() local
984 return DAG.getNode(ExtOpc, dl, PVT, Op); in PromoteOperand()
5838 unsigned ExtOpc, in ExtendUsesToFormExtLoad() argument
5852 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
5854 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 16945 static SDValue SplitAndExtendv16i1(unsigned ExtOpc, MVT VT, SDValue In, in SplitAndExtendv16i1() argument
16952 Lo = DAG.getNode(ExtOpc, dl, MVT::v8i16, Lo); in SplitAndExtendv16i1()
16953 Hi = DAG.getNode(ExtOpc, dl, MVT::v8i16, Hi); in SplitAndExtendv16i1()
19275 unsigned ExtOpc = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG ? in LowerEXTEND_VECTOR_INREG() local
19277 return DAG.getNode(ExtOpc, dl, VT, In); in LowerEXTEND_VECTOR_INREG()
23614 unsigned ExtOpc = in LowerShift() local
23616 R = DAG.getNode(ExtOpc, dl, ExtVT, R); in LowerShift()
36755 unsigned ExtOpc = LHS.getOpcode(); in combinePMULH() local
36756 if ((ExtOpc != ISD::SIGN_EXTEND && ExtOpc != ISD::ZERO_EXTEND) || in combinePMULH()
36757 RHS.getOpcode() != ExtOpc) in combinePMULH()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 20340 unsigned ExtOpc = in LowerShift() local
20342 R = DAG.getNode(ExtOpc, dl, ExtVT, R); in LowerShift()
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