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Searched refs:ExtType (Results 1 – 25 of 67) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonBitTracker.h50 struct ExtType { struct
54 ExtType() : Type(0), Width(0) {} in ExtType() argument
55 ExtType(char t, uint16_t w) : Type(t), Width(w) {} in ExtType() function
58 typedef DenseMap<unsigned, ExtType> RegExtMap;
DHexagonISelDAGToDAG.cpp250 ISD::LoadExtType ExtType = LD->getExtensionType(); in SelectIndexedLoad() local
251 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
304 auto getExt64 = [this,ExtType] (MachineSDNode *N, const SDLoc &dl) in SelectIndexedLoad()
306 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) { in SelectIndexedLoad()
311 if (ExtType == ISD::SEXTLOAD) in SelectIndexedLoad()
322 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in SelectIndexedLoad()
DHexagonBitTracker.cpp71 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width))); in HexagonEvaluator()
73 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width))); in HexagonEvaluator()
1120 if (F->second.Type == ExtType::SExt) in evaluateFormalCopy()
1122 else if (F->second.Type == ExtType::ZExt) in evaluateFormalCopy()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonBitTracker.h62 struct ExtType { struct
65 ExtType() = default;
66 ExtType(char t, uint16_t w) : Type(t), Width(w) {} in ExtType() function
72 using RegExtMap = DenseMap<unsigned, ExtType>;
DHexagonBitTracker.cpp84 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width))); in HexagonEvaluator()
86 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width))); in HexagonEvaluator()
1232 if (F->second.Type == ExtType::SExt) in evaluateFormalCopy()
1234 else if (F->second.Type == ExtType::ZExt) in evaluateFormalCopy()
DHexagonISelDAGToDAG.cpp77 ISD::LoadExtType ExtType = LD->getExtensionType(); in SelectIndexedLoad() local
78 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
133 auto getExt64 = [this,ExtType] (MachineSDNode *N, const SDLoc &dl) in SelectIndexedLoad()
135 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) { in SelectIndexedLoad()
140 if (ExtType == ISD::SEXTLOAD) in SelectIndexedLoad()
151 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in SelectIndexedLoad()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetLowering.h397 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const { in getLoadExtAction() argument
398 assert(ExtType < ISD::LAST_LOADEXT_TYPE && in getLoadExtAction()
401 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; in getLoadExtAction()
406 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { in isLoadExtLegal() argument
407 return VT.isSimple() && getLoadExtAction(ExtType, VT) == Legal; in isLoadExtLegal()
1063 void setLoadExtAction(unsigned ExtType, MVT VT, in setLoadExtAction() argument
1065 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && in setLoadExtAction()
1067 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; in setLoadExtAction()
/external/llvm/include/llvm/Target/
DTargetLowering.h657 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, in getLoadExtAction() argument
662 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE && in getLoadExtAction()
664 unsigned Shift = 4 * ExtType; in getLoadExtAction()
669 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegal() argument
670 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal; in isLoadExtLegal()
675 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegalOrCustom() argument
676 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal || in isLoadExtLegalOrCustom()
677 getLoadExtAction(ExtType, ValVT, MemVT) == Custom; in isLoadExtLegalOrCustom()
1433 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, in setLoadExtAction() argument
1435 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() && in setLoadExtAction()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetLowering.h944 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, in getLoadExtAction() argument
949 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE && in getLoadExtAction()
951 unsigned Shift = 4 * ExtType; in getLoadExtAction()
956 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegal() argument
957 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal; in isLoadExtLegal()
962 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegalOrCustom() argument
963 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal || in isLoadExtLegalOrCustom()
964 getLoadExtAction(ExtType, ValVT, MemVT) == Custom; in isLoadExtLegalOrCustom()
1806 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, in setLoadExtAction() argument
1808 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() && in setLoadExtAction()
[all …]
DSelectionDAG.h1055 getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain,
1060 SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT,
1065 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
1071 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1098 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); in printArithExtend() local
1104 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1108 ExtType == AArch64_AM::UXTX) || in printArithExtend()
1110 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
1116 O << ", " << AArch64_AM::getShiftExtendName(ExtType); in printArithExtend()
/external/capstone/arch/AArch64/
DAArch64InstPrinter.c809 AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val); in printArithExtend() local
815 if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) { in printArithExtend()
819 ExtType == AArch64_AM_UXTX) || in printArithExtend()
821 ExtType == AArch64_AM_UXTW) ) { in printArithExtend()
835 SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType)); in printArithExtend()
838 switch(ExtType) { in printArithExtend()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp956 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); in printArithExtend() local
962 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
966 ExtType == AArch64_AM::UXTX) || in printArithExtend()
968 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
974 O << ", " << AArch64_AM::getShiftExtendName(ExtType); in printArithExtend()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp204 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp() local
205 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
513 ISD::LoadExtType ExtType = LD->getExtensionType(); in ExpandLoad() local
602 switch (ExtType) { in ExpandLoad()
DLegalizeVectorTypes.cpp1049 ISD::LoadExtType ExtType = LD->getExtensionType(); in SplitVecRes_LOAD() local
1063 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1070 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1096 ISD::LoadExtType ExtType = MLD->getExtensionType(); in SplitVecRes_MLOAD() local
1127 ExtType); in SplitVecRes_MLOAD()
1139 ExtType); in SplitVecRes_MLOAD()
2839 ISD::LoadExtType ExtType = LD->getExtensionType(); in WidenVecRes_LOAD() local
2843 if (ExtType != ISD::NON_EXTLOAD) in WidenVecRes_LOAD()
2844 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); in WidenVecRes_LOAD()
2870 ISD::LoadExtType ExtType = N->getExtensionType(); in WidenVecRes_MLOAD() local
[all …]
DLegalizeDAG.cpp625 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeLoadOps() local
626 if (ExtType == ISD::NON_EXTLOAD) { in LegalizeLoadOps()
693 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) == in LegalizeLoadOps()
705 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
715 if (ExtType == ISD::SEXTLOAD) in LegalizeLoadOps()
720 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeLoadOps()
756 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
778 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
811 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0), in LegalizeLoadOps()
846 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) { in LegalizeLoadOps()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp1201 ISD::LoadExtType ExtType = LD->getExtensionType(); in SplitVecRes_LOAD() local
1213 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1218 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1243 ISD::LoadExtType ExtType = MLD->getExtensionType(); in SplitVecRes_MLOAD() local
1274 ExtType, MLD->isExpandingLoad()); in SplitVecRes_MLOAD()
1286 ExtType, MLD->isExpandingLoad()); in SplitVecRes_MLOAD()
2976 ISD::LoadExtType ExtType = LD->getExtensionType(); in WidenVecRes_LOAD() local
2980 if (ExtType != ISD::NON_EXTLOAD) in WidenVecRes_LOAD()
2981 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); in WidenVecRes_LOAD()
3007 ISD::LoadExtType ExtType = N->getExtensionType(); in WidenVecRes_MLOAD() local
[all …]
DLegalizeVectorOps.cpp232 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp() local
233 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) { in LegalizeOp()
575 ISD::LoadExtType ExtType = LD->getExtensionType(); in ExpandLoad() local
660 switch (ExtType) { in ExpandLoad()
DLegalizeDAG.cpp656 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeLoadOps() local
657 if (ExtType == ISD::NON_EXTLOAD) { in LegalizeLoadOps()
724 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) == in LegalizeLoadOps()
736 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
744 if (ExtType == ISD::SEXTLOAD) in LegalizeLoadOps()
749 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeLoadOps()
784 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
806 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
838 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0), in LegalizeLoadOps()
873 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) { in LegalizeLoadOps()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp1133 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp() local
1134 if (ExtType == ISD::NON_EXTLOAD) { in LegalizeOp()
1203 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { in LegalizeOp()
1214 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeOp()
1222 if (ExtType == ISD::SEXTLOAD) in LegalizeOp()
1227 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeOp()
1261 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, in LegalizeOp()
1282 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, in LegalizeOp()
1313 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { in LegalizeOp()
1357 switch (ExtType) { in LegalizeOp()
[all …]
DLegalizeVectorTypes.cpp708 ISD::LoadExtType ExtType = LD->getExtensionType(); in SplitVecRes_LOAD() local
720 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
727 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1879 ISD::LoadExtType ExtType = LD->getExtensionType(); in WidenVecRes_LOAD() local
1883 if (ExtType != ISD::NON_EXTLOAD) in WidenVecRes_LOAD()
1884 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); in WidenVecRes_LOAD()
2398 ISD::LoadExtType ExtType) { in GenWidenVectorExtLoads() argument
2421 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, in GenWidenVectorExtLoads()
2429 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, in GenWidenVectorExtLoads()
DLegalizeIntegerTypes.cpp414 ISD::LoadExtType ExtType = in PromoteIntRes_LOAD() local
417 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), in PromoteIntRes_LOAD()
1777 ISD::LoadExtType ExtType = N->getExtensionType(); in ExpandIntRes_LOAD() local
1788 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), in ExpandIntRes_LOAD()
1794 if (ExtType == ISD::SEXTLOAD) { in ExpandIntRes_LOAD()
1800 } else if (ExtType == ISD::ZEXTLOAD) { in ExpandIntRes_LOAD()
1804 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); in ExpandIntRes_LOAD()
1821 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, in ExpandIntRes_LOAD()
1839 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), in ExpandIntRes_LOAD()
1866 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, in ExpandIntRes_LOAD()
/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h922 SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT,
927 SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT,
932 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
938 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DSelectionDAG.h655 SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
662 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
668 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h140 ISD::LoadExtType ExtType,

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