| /external/vixl/src/aarch64/ |
| D | decoder-aarch64.cc | 36 if (instr->ExtractBits(28, 27) == 0) { in DecodeInstruction()
39 switch (instr->ExtractBits(27, 24)) { in DecodeInstruction()
178 VIXL_ASSERT(instr->ExtractBits(27, 24) == 0x0); in DecodePCRelAddressing()
187 VIXL_ASSERT((instr->ExtractBits(27, 24) == 0x4) || in DecodeBranchSystemException()
188 (instr->ExtractBits(27, 24) == 0x5) || in DecodeBranchSystemException()
189 (instr->ExtractBits(27, 24) == 0x6) || in DecodeBranchSystemException()
190 (instr->ExtractBits(27, 24) == 0x7)); in DecodeBranchSystemException()
192 switch (instr->ExtractBits(31, 29)) { in DecodeBranchSystemException()
223 if ((instr->ExtractBits(4, 2) != 0) || in DecodeBranchSystemException()
237 if (instr->ExtractBits(23, 22) == 0) { in DecodeBranchSystemException()
[all …]
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| D | constants-aarch64.h | 54 V_(Rd, 4, 0, ExtractBits) /* Destination register. */ \
55 V_(Rn, 9, 5, ExtractBits) /* First source register. */ \
56 V_(Rm, 20, 16, ExtractBits) /* Second source register. */ \
57 V_(Ra, 14, 10, ExtractBits) /* Third source register. */ \
58 V_(Rt, 4, 0, ExtractBits) /* Load/store register. */ \
59 V_(Rt2, 14, 10, ExtractBits) /* Load/store second register. */ \
60 V_(Rs, 20, 16, ExtractBits) /* Exclusive access status. */ \
63 V_(SixtyFourBits, 31, 31, ExtractBits) \
64 V_(FlagsUpdate, 29, 29, ExtractBits) \
68 V_(ImmPCRelLo, 30, 29, ExtractBits) \
[all …]
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| D | instructions-aarch64.h | 172 uint32_t ExtractBits(int msb, int lsb) const { in ExtractBits() function
176 return ExtractBits(msb, lsb);
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| D | simulator-aarch64.h | 513 uint32_t ExtractBits(int msb, int lsb) const { in ExtractBits() function
517 return ExtractBits(msb, lsb);
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| D | simulator-aarch64.cc | 5003 if ((instr->ExtractBit(23) == 0) && (instr->ExtractBits(20, 16) != 0)) { in NEONLoadStoreMultiStructHelper()
5149 if ((instr->ExtractBit(23) == 0) && (instr->ExtractBits(20, 16) != 0)) { in NEONLoadStoreSingleStructHelper()
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| D | disasm-aarch64.cc | 2703 unsigned index = (instr->ExtractBits(15, 11) << 2) | in VisitNEON3Same()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULowerKernelArguments.cpp | 203 Value *ExtractBits = OffsetDiff == 0 ? in runOnFunction() local
207 Value *Trunc = Builder.CreateTrunc(ExtractBits, ArgIntTy); in runOnFunction()
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| /external/mdnsresponder/mDNSShared/ |
| D | CommonServices.h | 700 #define ExtractBits( X, MASK, SHIFT ) ( ( ( X ) >> ( SHIFT ) ) & ( ( MASK ) >> ( SHIFT ) ) ) macro
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| /external/vixl/src/ |
| D | utils-vixl.h | 607 inline Td ExtractBits(Ts value, int least_significant_bit, Td mask) { in ExtractBits() function
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| /external/v8/src/compiler/mips/ |
| D | code-generator-mips.cc | 366 __ ExtractBits(i.OutputRegister(0), i.TempRegister(1), i.TempRegister(3), \
400 __ ExtractBits(i.OutputRegister(0), i.TempRegister(2), i.TempRegister(1), \
438 __ ExtractBits(i.OutputRegister(0), i.TempRegister(2), i.TempRegister(1), \
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| /external/v8/src/compiler/mips64/ |
| D | code-generator-mips64.cc | 377 __ ExtractBits(i.OutputRegister(0), i.TempRegister(1), i.TempRegister(3), \
412 __ ExtractBits(i.OutputRegister(0), i.TempRegister(2), i.TempRegister(1), \
451 __ ExtractBits(i.OutputRegister(0), i.TempRegister(2), i.TempRegister(1), \
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| /external/v8/src/mips/ |
| D | macro-assembler-mips.h | 608 void ExtractBits(Register dest, Register source, Register pos, int size,
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| D | macro-assembler-mips.cc | 1681 void TurboAssembler::ExtractBits(Register dest, Register source, Register pos, in ExtractBits() function in v8::internal::TurboAssembler
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| /external/v8/src/mips64/ |
| D | macro-assembler-mips64.h | 598 void ExtractBits(Register dest, Register source, Register pos, int size,
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| D | macro-assembler-mips64.cc | 2039 void TurboAssembler::ExtractBits(Register dest, Register source, Register pos, in ExtractBits() function in v8::internal::TurboAssembler
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