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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
Dfloating-point-arithmetic.ll189 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
190 ; CHECK-NEXT: ret float [[FABS]]
202 ; CHECK-NEXT: [[FABS:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[SELECT]])
203 ; CHECK-NEXT: ret <2 x float> [[FABS]]
215 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
216 ; CHECK-NEXT: ret float [[FABS]]
228 ; CHECK-NEXT: [[FABS:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[SELECT]])
229 ; CHECK-NEXT: ret <2 x float> [[FABS]]
241 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
242 ; CHECK-NEXT: ret float [[FABS]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dfabs.ll27 ; CHECK-NEXT: [[FABS:%.*]] = call double @llvm.fabs.f64(double [[X:%.*]])
28 ; CHECK-NEXT: ret double [[FABS]]
72 ; CHECK-NEXT: [[FABS:%.*]] = tail call double @llvm.fabs.f64(double [[MUL]])
73 ; CHECK-NEXT: ret double [[FABS]]
132 ; CHECK-NEXT: [[FABS:%.*]] = select i1 [[CMP]], float 1.000000e+00, float 2.000000e+00
133 ; CHECK-NEXT: ret float [[FABS]]
144 ; CHECK-NEXT: [[FABS:%.*]] = select i1 [[CMP]], float 1.000000e+00, float 2.000000e+00
145 ; CHECK-NEXT: ret float [[FABS]]
156 ; CHECK-NEXT: [[FABS:%.*]] = select i1 [[CMP]], float 1.000000e+00, float 2.000000e+00
157 ; CHECK-NEXT: ret float [[FABS]]
[all …]
Dfast-math.ll842 ; CHECK-NEXT: [[FABS:%.*]] = call fast double @llvm.fabs.f64(double [[X:%.*]])
843 ; CHECK-NEXT: ret double [[FABS]]
855 ; CHECK-NEXT: [[FABS:%.*]] = call fast double @llvm.fabs.f64(double [[X:%.*]])
857 ; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
868 ; CHECK-NEXT: [[FABS:%.*]] = call fast double @llvm.fabs.f64(double [[X:%.*]])
870 ; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
881 ; CHECK-NEXT: [[FABS:%.*]] = call fast double @llvm.fabs.f64(double [[X:%.*]])
883 ; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
894 ; CHECK-NEXT: [[FABS:%.*]] = call fast double @llvm.fabs.f64(double [[X:%.*]])
896 ; CHECK-NEXT: [[TMP1:%.*]] = fmul fast double [[FABS]], [[SQRT1]]
[all …]
Dfloat-shrink-compare.ll33 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float %x)
34 ; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FABS]], %y
46 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float %x)
47 ; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FABS]], %y
216 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float %x)
217 ; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FABS]], %y
229 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float %x)
230 ; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[FABS]], %y
Dpow-1.ll132 ; CHECK-NEXT: [[FABS:%[a-z0-9]+]] = call double @llvm.fabs.f64(double [[SQRT]])
134 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], double 0x7FF0000000000000, double [[FABS]]
276 ; CHECK-NEXT: [[FABS:%[a-z0-9]+]] = call double @llvm.fabs.f64(double [[SQRT]])
278 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], double 0x7FF0000000000000, double [[FABS]]
/external/llvm/test/Transforms/InstCombine/
Dpow-1.ll86 ; CHECK-NEXT: [[FABS:%[a-z0-9]+]] = call double @fabs(double [[SQRT]]) [[NUW_RO]]
88 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], double 0x7FF0000000000000, double [[FABS]]
166 ; CHECK-NEXT: [[FABS:%[a-z0-9]+]] = call double @fabs(double [[SQRT]])
168 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], double 0x7FF0000000000000, double [[FABS]]
/external/llvm/test/CodeGen/X86/
Dfnabs.ll4 ; FNABS(x) operation -> FNEG (FABS(x)).
5 ; If the FABS() result isn't used, the AND instruction should be eliminated.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dfnabs.ll4 ; FNABS(x) operation -> FNEG (FABS(x)).
5 ; If the FABS() result isn't used, the AND instruction should be eliminated.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dfabs.f16.ll117 ; GFX9: v_and_b32_e32 [[FABS:v[0-9]+]], 0x7fff7fff, [[VAL]]
118 ; GFX9: v_pk_mul_f16 v{{[0-9]+}}, [[FABS]], v{{[0-9]+$}}
144 ; GFX9: v_and_b32_e32 [[FABS:v[0-9]+]], 0x7fff7fff, [[VAL]]
145 ; GFX9: v_pk_mul_f16 v{{[0-9]+}}, [[FABS]], s{{[0-9]+$}}
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp1010 if ((Opc == ISD::FABS || Opc == ISD::FNEG) && !HST->hasV5TOps()) { in SelectBitOp()
1016 if (Opc != ISD::FABS && Opc != ISD::FNEG) { in SelectBitOp()
1053 if (Opc != ISD::FABS && Opc != ISD::FNEG) { in SelectBitOp()
1073 case ISD::FABS: in SelectBitOp()
1124 if (Opc != ISD::FABS && Opc != ISD::FNEG) in SelectBitOp()
1231 case ISD::FABS: in Select()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h450 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h524 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h557 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp309 setOperationAction(ISD::FABS, MVT::f32, Legal); in AMDGPUTargetLowering()
445 setOperationAction(ISD::FABS, VT, Expand); in AMDGPUTargetLowering()
534 setTargetDAGCombine(ISD::FABS); in AMDGPUTargetLowering()
1517 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr); in LowerDIVREM24()
1520 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb); in LowerDIVREM24()
2057 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFRINT()
2092 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff); in LowerFROUND32_16()
3352 if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) || in foldFreeOpFromSelect()
3359 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) { in foldFreeOpFromSelect()
3366 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) { in foldFreeOpFromSelect()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp76 case ISD::FABS: R = SoftenFloatRes_FABS(N, ResNo); break; in SoftenFloatResult()
801 case ISD::FABS: in CanSkipSoftenFloatOperand()
816 case ISD::FABS: in CanSkipSoftenFloatOperand()
1016 case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break; in ExpandFloatResult()
1076 Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp); in ExpandFloatRes_FABS()
1869 case ISD::FABS: in PromoteFloatResult()
DSelectionDAGDumper.cpp152 case ISD::FABS: return "fabs"; in getOperationName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp76 case ISD::FABS: R = SoftenFloatRes_FABS(N, ResNo); break; in SoftenFloatResult()
758 case ISD::FABS: Res = SoftenFloatOp_FABS(N); break; in SoftenFloatOperand()
807 case ISD::FABS: in CanSkipSoftenFloatOperand()
1070 case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break; in ExpandFloatResult()
1130 Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp); in ExpandFloatRes_FABS()
1887 case ISD::FABS: in PromoteFloatResult()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp173 case ISD::FABS: in LegalizeOp()
DDAGCombiner.cpp1100 case ISD::FABS: return visitFABS(N); in visit()
5020 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && in visitBITCAST()
5030 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
5422 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) in visitFCOPYSIGN()
5423 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); in visitFCOPYSIGN()
5427 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); in visitFCOPYSIGN()
5434 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || in visitFCOPYSIGN()
5440 if (N1.getOpcode() == ISD::FABS) in visitFCOPYSIGN()
5441 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); in visitFCOPYSIGN()
5663 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); in visitFABS()
[all …]
DLegalizeFloatTypes.cpp66 case ISD::FABS: R = SoftenFloatRes_FABS(N); break; in SoftenFloatResult()
849 case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break; in ExpandFloatResult()
902 Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp); in ExpandFloatRes_FABS()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUInstructions.td455 class FABS <RegisterClass rc> : AMDGPUShaderInst <
458 "FABS $dst, $src0",
DAMDGPUISelLowering.cpp242 setOperationAction(ISD::FABS, MVT::f32, Legal); in AMDGPUTargetLowering()
407 setOperationAction(ISD::FABS, VT, Expand); in AMDGPUTargetLowering()
1299 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr); in LowerDIVREM24()
1302 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb); in LowerDIVREM24()
1707 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFRINT()
1737 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff); in LowerFROUND32()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1663 setOperationAction(ISD::FABS, MVT::f64, Custom); in SparcTargetLowering()
1752 setOperationAction(ISD::FABS, MVT::f128, Legal); in SparcTargetLowering()
1755 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1774 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
2704 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2864 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
3073 case ISD::FABS: in LowerOperation()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1658 setOperationAction(ISD::FABS, MVT::f64, Custom); in SparcTargetLowering()
1765 setOperationAction(ISD::FABS, MVT::f128, Legal); in SparcTargetLowering()
1768 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1787 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
2753 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2898 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
3107 case ISD::FABS: in LowerOperation()
/external/v8/src/ppc/
Ddisasm-ppc.cc1054 case FABS: { in DecodeExt4()

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