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Searched refs:FAND (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h392 X86_INTRINSIC_DATA(avx512_mask_and_pd_128, INTR_TYPE_2OP_MASK, X86ISD::FAND, 0),
393 X86_INTRINSIC_DATA(avx512_mask_and_pd_256, INTR_TYPE_2OP_MASK, X86ISD::FAND, 0),
394 X86_INTRINSIC_DATA(avx512_mask_and_pd_512, INTR_TYPE_2OP_MASK, X86ISD::FAND, 0),
395 X86_INTRINSIC_DATA(avx512_mask_and_ps_128, INTR_TYPE_2OP_MASK, X86ISD::FAND, 0),
396 X86_INTRINSIC_DATA(avx512_mask_and_ps_256, INTR_TYPE_2OP_MASK, X86ISD::FAND, 0),
397 X86_INTRINSIC_DATA(avx512_mask_and_ps_512, INTR_TYPE_2OP_MASK, X86ISD::FAND, 0),
DX86ISelLowering.h45 FAND, enumerator
DX86InstrFragmentsSIMD.td53 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
DX86ISelLowering.cpp7424 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND, in lowerVectorShuffleAsBitMask()
14362 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR; in LowerFABSorFNEG()
14428 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1); in LowerFCOPYSIGN()
14456 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val); in LowerFCOPYSIGN()
15293 CombineOpc = Opc == X86ISD::CMPP ? static_cast<unsigned>(X86ISD::FAND) : in LowerVSETCC()
15783 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1); in LowerSELECT()
22082 case X86ISD::FAND: return "X86ISD::FAND"; in getTargetNodeName()
26276 case ISD::AND: FPOpcode = X86ISD::FAND; break; in combineBitcast()
28172 FPOpcode = X86ISD::FAND; in convertIntLogicToFPLogic()
29793 case X86ISD::FAND: IntOpcode = ISD::AND; break; in lowerX86FPLogicOp()
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/external/llvm/lib/Target/Sparc/
DSparcInstrVIS.td102 def FAND : VISInst<0b001110000, "fand">;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrVIS.td102 def FAND : VISInst<0b001110000, "fand">;
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.h46 FAND, enumerator
DX86InstrFragmentsSIMD.td43 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
DX86ISelLowering.cpp8027 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); in LowerFABS()
8103 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); in LowerFCOPYSIGN()
8132 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); in LowerFCOPYSIGN()
10625 case X86ISD::FAND: return "X86ISD::FAND"; in getTargetNodeName()
14219 case X86ISD::FAND: return PerformFANDCombine(N, DAG); in PerformDAGCombine()
DX86GenFastISel.inc2487 // FastEmit functions for X86ISD::FAND.
3686 case X86ISD::FAND: return FastEmit_X86ISD_FAND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
DX86GenDAGISel.inc39174 /*SwitchOpcode*/ 23|128,2/*279*/, TARGET_VAL(X86ISD::FAND),// ->81952
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelLowering.h45 FAND, enumerator
DX86InstrFragmentsSIMD.td50 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
DX86ISelLowering.cpp17463 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR; in LowerFABSorFNEG()
17524 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Sign, SignMask); in LowerFCOPYSIGN()
17538 MagBits = DAG.getNode(X86ISD::FAND, dl, LogicVT, Mag, MagMask); in LowerFCOPYSIGN()
18414 CombineOpc = X86ISD::FAND; in LowerVSETCC()
18877 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1); in LowerSELECT()
25900 case X86ISD::FAND: return "X86ISD::FAND"; in getTargetNodeName()
29929 FloatDomain ? unsigned(X86ISD::FAND) : unsigned(ISD::AND); in combineX86ShuffleChain()
31777 case ISD::AND: FPOpcode = X86ISD::FAND; break; in combineBitcast()
34585 FPOpcode = X86ISD::FAND; in convertIntLogicToFPLogic()
34772 MVT::v4i32, DAG.getNode(X86ISD::FAND, SDLoc(N), MVT::v4f32, in combineAnd()
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/external/capstone/arch/Sparc/
DSparcGenDisassemblerTables.inc1139 /* 4548 */ MCD_OPC_Decode, 143, 1, 27, // Opcode: FAND
DSparcGenAsmWriter.inc164 4875U, // FAND
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc8752 // FastEmit functions for X86ISD::FAND.
11994 case X86ISD::FAND: return fastEmit_X86ISD_FAND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);