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Searched refs:FDIV_S (Results 1 – 17 of 17) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoF.td118 def FDIV_S : FPALUS_rr_frm<0b0001100, "fdiv.s">;
119 def : FPALUSDynFrmAlias<FDIV_S, "fdiv.s">;
268 def : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>;
/external/mesa3d/src/mesa/x86/
Dx86_cliptest.S166 FDIV_S( SRC3 ) /* GH: don't care about div-by-zero */
Dassyntax.h710 #define FDIV_S(a) CHOICE(fdivs a, fdivs a, fdivs a) macro
1423 #define FDIV_S(a) fdiv S_(a) macro
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsScheduleP5600.td443 def : InstRW<[P5600WriteFPUDivS], (instrs FDIV_S)>;
DMipsInstrFPU.td604 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
/external/llvm/lib/Target/Mips/
DMipsInstrFPU.td471 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc893 {DBGFIELD("FDIV_S") 1, false, false, 24, 2, 10, 1, 0, 0}, // #618
1913 {DBGFIELD("FDIV_S") 1, false, false, 55, 3, 15, 1, 0, 0}, // #618
DMipsGenMCCodeEmitter.inc1403 UINT64_C(1174405123), // FDIV_S
3257 case Mips::FDIV_S:
9129 Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FDIV_S = 1390
DMipsGenInstrInfo.inc1405 FDIV_S = 1390,
3275 FDIV_S = 618,
5450 …, 3, 1, 4, 618, 0, 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1390 = FDIV_S
10129 { Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM },
DMipsGenAsmWriter.inc2618 268459274U, // FDIV_S
5249 0U, // FDIV_S
DMipsGenFastISel.inc1511 return fastEmitInst_rr(Mips::FDIV_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenGlobalISel.inc14473 …// (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] …
14474 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S,
DMipsGenDisassemblerTables.inc3318 /* 2667 */ MCD::OPC_Decode, 238, 10, 204, 1, // Opcode: FDIV_S
DMipsGenAsmMatcher.inc5965 …{ 3212 /* div.s */, Mips::FDIV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature…
DMipsGenDAGISel.inc27948 /* 52522*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FDIV_S), 0,
27951 // Dst: (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc718 33577469U, // FDIV_S
2432 0U, // FDIV_S
DMipsGenDisassemblerTables.inc861 /* 1829 */ MCD_OPC_Decode, 189, 5, 70, // Opcode: FDIV_S