/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 532 FMINNUM, FMAXNUM, enumerator
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D | BasicTTIImpl.h | 774 ISDs.push_back(ISD::FMAXNUM); in getIntrinsicInstrCost()
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D | SelectionDAG.h | 1187 case ISD::FMAXNUM:
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 565 FMINNUM, FMAXNUM, enumerator
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D | BasicTTIImpl.h | 1045 ISDs.push_back(ISD::FMAXNUM);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
D | PPCCTRLoops.cpp | 335 case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break; in mightUseCTR() 404 Opcode = ISD::FMAXNUM; break; in mightUseCTR()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCCTRLoops.cpp | 309 case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break; in mightUseCTR() 376 Opcode = ISD::FMAXNUM; break; in mightUseCTR()
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/external/llvm/lib/Target/AMDGPU/ |
D | SIISelLowering.cpp | 206 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in SITargetLowering() 224 setTargetDAGCombine(ISD::FMAXNUM); in SITargetLowering() 1711 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp, in LowerINTRINSIC_WO_CHAIN() 2693 case ISD::FMAXNUM: in minMaxOpcToMin3Max3Opc() 2816 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) || in performMinMaxCombine() 2868 case ISD::FMAXNUM: in PerformDAGCombine()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 154 case ISD::FMAXNUM: return "fmaxnum"; in getOperationName()
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D | LegalizeFloatTypes.cpp | 78 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break; in SoftenFloatResult() 1018 case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break; in ExpandFloatResult() 1891 case ISD::FMAXNUM: in PromoteFloatResult()
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D | LegalizeVectorOps.cpp | 304 case ISD::FMAXNUM: in LegalizeOp()
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D | SelectionDAGBuilder.cpp | 2802 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break; in visitSelect() 2805 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT)) in visitSelect() 2806 Opc = ISD::FMAXNUM; in visitSelect() 2810 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ? in visitSelect() 2811 ISD::FMAXNUM : ISD::FMAXNAN; in visitSelect() 5222 : ISD::FMAXNUM; in visitIntrinsicCall() 6255 if (visitBinaryFloatCall(I, ISD::FMAXNUM)) in visitCall()
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D | LegalizeVectorTypes.cpp | 111 case ISD::FMAXNUM: in ScalarizeVectorResult() 676 case ISD::FMAXNUM: in SplitVectorResult() 2092 case ISD::FMAXNUM: in WidenVectorResult()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | SIISelLowering.cpp | 379 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in SITargetLowering() 468 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); in SITargetLowering() 570 setOperationAction(ISD::FMAXNUM, MVT::v2f16, Legal); in SITargetLowering() 591 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Custom); in SITargetLowering() 625 setTargetDAGCombine(ISD::FMAXNUM); in SITargetLowering() 3643 case ISD::FMAXNUM: in LowerOperation() 4814 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp, in LowerINTRINSIC_WO_CHAIN() 6719 case ISD::FMAXNUM: in fp16SrcZerosHighBits() 6852 case ISD::FMAXNUM: in isCanonicalized() 6945 case ISD::FMAXNUM: in minMaxOpcToMin3Max3Opc() [all …]
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D | AMDGPUISelLowering.cpp | 314 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in AMDGPUTargetLowering() 447 setOperationAction(ISD::FMAXNUM, VT, Expand); in AMDGPUTargetLowering() 552 case ISD::FMAXNUM: in fnegFoldsIntoOp() 3460 case ISD::FMAXNUM: in inverseMinMax() 3463 return ISD::FMAXNUM; in inverseMinMax() 3567 case ISD::FMAXNUM: in performFNegCombine()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 177 case ISD::FMAXNUM: return "fmaxnum"; in getOperationName()
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D | LegalizeFloatTypes.cpp | 78 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break; in SoftenFloatResult() 1072 case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break; in ExpandFloatResult() 1910 case ISD::FMAXNUM: in PromoteFloatResult()
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D | LegalizeVectorTypes.cpp | 115 case ISD::FMAXNUM: in ScalarizeVectorResult() 733 case ISD::FMAXNUM: in SplitVectorResult() 1749 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXNAN; in SplitVecOp_VECREDUCE() 2300 case ISD::FMAXNUM: in WidenVectorResult()
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D | LegalizeVectorOps.cpp | 363 case ISD::FMAXNUM: in LegalizeOp()
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D | SelectionDAGBuilder.cpp | 2981 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break; in visitSelect() 2984 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT)) in visitSelect() 2985 Opc = ISD::FMAXNUM; in visitSelect() 2989 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ? in visitSelect() 2990 ISD::FMAXNUM : ISD::FMAXNAN; in visitSelect() 5569 : ISD::FMAXNUM; in visitIntrinsicCall() 6911 if (visitBinaryFloatCall(I, ISD::FMAXNUM)) in visitCall()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
D | RISCVISelLowering.cpp | 116 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in RISCVTargetLowering() 126 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in RISCVTargetLowering()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 293 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); in AArch64TargetLowering() 385 setOperationAction(ISD::FMAXNUM, Ty, Legal); in AArch64TargetLowering() 705 ISD::FMINNUM, ISD::FMAXNUM}) in addTypeForNEON() 8561 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine() 8952 if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) { in tryMatchAcrossLaneShuffleForReduction() 9029 case ISD::FMAXNUM: in tryMatchAcrossLaneShuffleForReduction() 9098 Op != ISD::UMIN && Op != ISD::FMAXNUM && Op != ISD::FMINNUM) in performAcrossLaneMinMaxReductionCombine() 9109 if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) { in performAcrossLaneMinMaxReductionCombine() 9133 (Op == ISD::FMAXNUM && CC != ISD::SETOGT && CC != ISD::SETOGE && in performAcrossLaneMinMaxReductionCombine()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
D | SystemZISelLowering.cpp | 454 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in SystemZTargetLowering() 459 setOperationAction(ISD::FMAXNUM, MVT::v2f64, Legal); in SystemZTargetLowering() 464 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in SystemZTargetLowering() 469 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in SystemZTargetLowering() 474 setOperationAction(ISD::FMAXNUM, MVT::f128, Legal); in SystemZTargetLowering()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
D | TargetLoweringBase.cpp | 601 setOperationAction(ISD::FMAXNUM, VT, Expand); in initActions()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | HexagonISelLowering.cpp | 1428 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering() 1524 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in HexagonTargetLowering()
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