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Searched refs:FMUL_S (Results 1 – 19 of 19) sorted by relevance

/external/mesa3d/src/mesa/x86/
Dx86_xform4.S101 FMUL_S( MAT0 )
103 FMUL_S( MAT1 )
105 FMUL_S( MAT2 )
107 FMUL_S( MAT3 )
110 FMUL_S( MAT4 )
112 FMUL_S( MAT5 )
114 FMUL_S( MAT6 )
116 FMUL_S( MAT7 )
126 FMUL_S( MAT8 )
128 FMUL_S( MAT9 )
[all …]
Dx86_xform3.S101 FMUL_S( MAT0 )
103 FMUL_S( MAT1 )
105 FMUL_S( MAT2 )
107 FMUL_S( MAT3 )
110 FMUL_S( MAT4 )
112 FMUL_S( MAT5 )
114 FMUL_S( MAT6 )
116 FMUL_S( MAT7 )
126 FMUL_S( MAT8 )
128 FMUL_S( MAT9 )
[all …]
Dx86_xform2.S101 FMUL_S( MAT0 )
103 FMUL_S( MAT1 )
105 FMUL_S( MAT2 )
107 FMUL_S( MAT3 )
110 FMUL_S( MAT4 )
112 FMUL_S( MAT5 )
114 FMUL_S( MAT6 )
116 FMUL_S( MAT7 )
195 FMUL_S( MAT0 )
198 FMUL_S( MAT5 )
[all …]
Dassyntax.h749 #define FMUL_S(a) CHOICE(fmuls a, fmuls a, fmuls a) macro
1462 #define FMUL_S(a) fmul S_(a) macro
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoF.td116 def FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">;
117 def : FPALUSDynFrmAlias<FMUL_S, "fmul.s">;
267 def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsScheduleP5600.td433 (instrs FADD_D32, FADD_D64, FADD_S, FMUL_D32, FMUL_D64, FMUL_S,
DMipsInstrFPU.td608 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
/external/llvm/lib/Target/Mips/
DMipsInstrFPU.td474 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc883 {DBGFIELD("FMUL_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #608
1903 {DBGFIELD("FMUL_S") 1, false, false, 58, 2, 6, 1, 0, 0}, // #608
DMipsGenMCCodeEmitter.inc1464 UINT64_C(1174405122), // FMUL_S
3260 case Mips::FMUL_S:
9190 Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FMUL_S = 1451
DMipsGenInstrInfo.inc1466 FMUL_S = 1451,
3265 FMUL_S = 608,
5511 …MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1451 = FMUL_S
10135 { Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM },
DMipsGenAsmWriter.inc2679 268459024U, // FMUL_S
5310 0U, // FMUL_S
DMipsGenFastISel.inc1571 return fastEmitInst_rr(Mips::FMUL_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenGlobalISel.inc14228 …// (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] …
14229 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S,
DMipsGenDisassemblerTables.inc3315 /* 2652 */ MCD::OPC_Decode, 171, 11, 204, 1, // Opcode: FMUL_S
DMipsGenAsmMatcher.inc6842 …{ 6828 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature…
DMipsGenDAGISel.inc28012 /* 52643*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMUL_S), 0,
28015 … // Dst: (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc775 33577229U, // FMUL_S
2489 0U, // FMUL_S
DMipsGenDisassemblerTables.inc858 /* 1817 */ MCD_OPC_Decode, 246, 5, 70, // Opcode: FMUL_S