| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-fpcr.ll | 5 ; CHECK: mrs x0, FPCR
15 ; CHECK: mrs x8, FPCR
|
| /external/v8/src/arm64/ |
| D | simulator-arm64.cc | 93 case FPCR: in DefaultValueFor()
350 fpcr_ = SimSystemRegister::DefaultValueFor(FPCR); in ResetState()
1105 PrintSystemRegister(FPCR); in PrintSystemRegisters()
1337 case FPCR: { in PrintSystemRegister()
2947 case FPCR: set_xreg(instr->Rt(), fpcr().RawValue()); break; in VisitSystem()
2958 case FPCR: in VisitSystem()
2960 LogSystemRegister(FPCR); in VisitSystem()
|
| D | constants-arm64.h | 284 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
418 FPCR = ((0x1 << SysO0_offset) | enumerator
|
| D | disasm-arm64.cc | 1226 case FPCR: form = "'Xt, fpcr"; break; in VisitSystem()
1235 case FPCR: form = "fpcr, 'Xt"; break; in VisitSystem()
|
| D | macro-assembler-arm64.cc | 1491 Mrs(fpcr, FPCR); in AssertFPCRState()
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.cc | 58 case FPCR: in DefaultValueFor()
120 fpcr_ = SimSystemRegister::DefaultValueFor(FPCR); in ResetState()
634 PrintSystemRegister(FPCR); in PrintSystemRegisters()
925 case FPCR: { in PrintSystemRegister()
3679 case FPCR: in VisitSystem()
3693 case FPCR: in VisitSystem()
3695 LogSystemRegister(FPCR); in VisitSystem()
|
| D | constants-aarch64.h | 191 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
365 FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value enumerator
|
| D | disasm-aarch64.cc | 5375 case FPCR: in SubstituteImmediateField()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAArch64.td | 591 // FPCR
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenSystemOperands.inc | 389 FPCR = 55840,
2216 { "FPCR", 0xDA20, true, true, {} }, // 234
2954 { "FPCR", 234 },
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | basic-a64-instructions.s | 3810 msr FPCR, x12
4358 mrs x9, FPCR
|
| /external/llvm/test/MC/AArch64/ |
| D | basic-a64-instructions.s | 3827 msr FPCR, x12
4375 mrs x9, FPCR
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaInstrInfo.td | 1033 //MF_FPCR F-P 17.025 Move from FPCR
1034 //MT_FPCR F-P 17.024 Move to FPCR
|
| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 14773 __ Mrs(x6, FPCR); in TEST()
14828 __ Msr(FPCR, x8); in TEST()
14829 __ Mrs(x8, FPCR); in TEST()
14835 __ Msr(FPCR, x9); in TEST()
14836 __ Mrs(x9, FPCR); in TEST()
14844 __ Msr(FPCR, x10); in TEST()
14845 __ Mrs(x10, FPCR); in TEST()
17429 __ Mrs(x0, FPCR); in DefaultNaNHelper()
17431 __ Msr(FPCR, x1); in DefaultNaNHelper()
17470 __ Msr(FPCR, x0); in DefaultNaNHelper()
[all …]
|
| D | test-disasm-aarch64.cc | 3141 COMPARE(mrs(x15, FPCR), "mrs x15, fpcr"); in TEST()
3156 COMPARE(msr(FPCR, x15), "msr fpcr, x15"); in TEST()
|
| D | test-cpu-features-aarch64.cc | 379 TEST_NONE(mrs_0, mrs(x0, FPCR))
380 TEST_NONE(msr_0, msr(FPCR, x0))
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SystemOperands.td | 578 def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SystemOperands.td | 748 def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>;
|
| D | AArch64InstrInfo.td | 623 // FPCR register
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | basic-a64-instructions.txt | 3300 # CHECK: msr {{fpcr|FPCR}}, x12
3592 # CHECK: mrs x9, {{fpcr|FPCR}}
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | basic-a64-instructions.txt | 3284 # CHECK: msr {{fpcr|FPCR}}, x12
3577 # CHECK: mrs x9, {{fpcr|FPCR}}
|