Home
last modified time | relevance | path

Searched refs:FPGA_GET_REG (Results 1 – 10 of 10) sorted by relevance

/external/u-boot/board/gdsys/common/
Dmclink.c33 FPGA_GET_REG(k, mc_status, &mc_status); in mclink_probe()
40 FPGA_GET_REG(k, mc_status, &mc_status); in mclink_probe()
47 FPGA_GET_REG(k, mc_status, &mc_status); in mclink_probe()
68 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
78 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
83 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
86 FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status); in mclink_send()
110 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
115 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
119 FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status); in mclink_receive()
[all …]
Dcmd_ioloop.c115 FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); in io_receive()
123 FPGA_GET_REG(fpga, ep.receive_data, &rx); in io_receive()
125 FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); in io_receive()
139 FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); in io_reflect()
142 FPGA_GET_REG(fpga, ep.receive_data, &buffer[k++]); in io_reflect()
146 FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); in io_reflect()
196 FPGA_GET_REG(fpga, top_interrupt, &top_int); in do_ioreflect()
197 FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); in do_ioreflect()
262 FPGA_GET_REG(fpga, top_interrupt, &top_int); in do_ioloop()
263 FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); in do_ioloop()
Dioep-fpga.c59 FPGA_GET_REG(0, fpga_features, &fpga_features); in ioep_fpga_has_osd()
81 FPGA_GET_REG(fpga, versions, &versions); in ioep_fpga_print_info()
82 FPGA_GET_REG(fpga, fpga_version, &fpga_version); in ioep_fpga_print_info()
83 FPGA_GET_REG(fpga, fpga_features, &fpga_features); in ioep_fpga_print_info()
Dihs_mdio.c54 FPGA_GET_REG(info->fpga, mdio.control, &val); in read_control()
83 FPGA_GET_REG(info->fpga, mdio.rx_data, &val); in read_rx_data()
Dosd.c54 FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
56 FPGA_GET_REG(screen, osd0.fld, val); \
60 FPGA_GET_REG(screen, osd0.fld, val)
/external/u-boot/board/gdsys/mpc8308/
Dhrcon.c130 FPGA_GET_REG(0, fpga_features, &fpga_features); in last_stage_init()
200 FPGA_GET_REG(k, fpga_features, &fpga_features); in last_stage_init()
250 FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val); in fpga_gpio_get()
259 FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val); in fpga_control_set()
267 FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val); in fpga_control_clear()
424 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); in mii_get_mdio()
Dstrider.c303 FPGA_GET_REG(bus, gpio.read, &val); in fpga_gpio_get()
313 FPGA_GET_REG(bus, control, &val); in fpga_control_set()
321 FPGA_GET_REG(bus, control, &val); in fpga_control_clear()
479 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); in mii_get_mdio()
Dmpc8308.c85 FPGA_GET_REG(k, REFLECTION_TESTREG, &val); in board_early_init_r()
/external/u-boot/drivers/i2c/
Dihs_i2c.c54 FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
56 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
60 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
/external/u-boot/include/
Dgdsys_fpga.h31 #define FPGA_GET_REG(ix, fld, val) \ macro