Home
last modified time | relevance | path

Searched refs:FPGA_SET_REG (Results 1 – 9 of 9) sorted by relevance

/external/u-boot/board/gdsys/common/
Dmclink.c38 FPGA_SET_REG(k, mc_control, 0x8000); in mclink_probe()
69 FPGA_SET_REG(0, mc_int, int_status); in mclink_send()
72 FPGA_SET_REG(0, mc_tx_address, addr); in mclink_send()
73 FPGA_SET_REG(0, mc_tx_data, data); in mclink_send()
74 FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14); in mclink_send()
75 FPGA_SET_REG(0, mc_control, 0x8001); in mclink_send()
103 FPGA_SET_REG(0, mc_tx_address, addr); in mclink_receive()
104 FPGA_SET_REG(0, mc_tx_cmd, in mclink_receive()
106 FPGA_SET_REG(0, mc_control, 0x8001); in mclink_receive()
Dcmd_ioloop.c62 FPGA_SET_REG(fpga, ep.rx_tx_status, status); in io_check_status()
67 FPGA_SET_REG(fpga, ep.rx_tx_status, status); in io_check_status()
99 FPGA_SET_REG(fpga, ep.transmit_data, *p++); in io_send()
102 FPGA_SET_REG(fpga, ep.transmit_data, k); in io_send()
104 FPGA_SET_REG(fpga, ep.rx_tx_control, in io_send()
153 FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]); in io_reflect()
155 FPGA_SET_REG(fpga, ep.rx_tx_control, in io_reflect()
185 FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE); in do_ioreflect()
188 FPGA_SET_REG(fpga, ep.device_address, 1); in do_ioreflect()
251 FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE); in do_ioloop()
[all …]
Dosd.c41 FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
43 FPGA_SET_REG(screen, osd0.fld, val); \
47 FPGA_SET_REG(screen, osd0.fld, val)
126 FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m); in mpc92469ac_set()
248 FPGA_SET_REG(screen - OSD_DH_BASE, in osd_write_videomem()
251 FPGA_SET_REG(screen, videomem0[offset + k], data[k]); in osd_write_videomem()
253 FPGA_SET_REG(screen, videomem0[offset + k], data[k]); in osd_write_videomem()
Dihs_mdio.c64 FPGA_SET_REG(info->fpga, mdio.control, val); in write_control()
73 FPGA_SET_REG(info->fpga, mdio.address_data, val); in write_addr_data()
/external/u-boot/board/gdsys/mpc8308/
Dstrider.c236 FPGA_SET_REG(k, extended_control, 0x10); /* enable video */ in last_stage_init()
291 FPGA_SET_REG(bus, gpio.set, pin); in fpga_gpio_set()
296 FPGA_SET_REG(bus, gpio.clear, pin); in fpga_gpio_clear()
314 FPGA_SET_REG(bus, control, val | pin); in fpga_control_set()
322 FPGA_SET_REG(bus, control, val & ~pin); in fpga_control_clear()
444 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_active()
446 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_mdio_active()
455 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_tristate()
465 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_set_mdio()
467 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_set_mdio()
[all …]
Dhrcon.c238 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin); in fpga_gpio_set()
243 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin); in fpga_gpio_clear()
260 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin); in fpga_control_set()
268 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin); in fpga_control_clear()
389 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_active()
391 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_mdio_active()
400 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_tristate()
410 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_set_mdio()
412 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_set_mdio()
436 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); in mii_set_mdc()
[all …]
Dmpc8308.c83 FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); in board_early_init_r()
/external/u-boot/drivers/i2c/
Dihs_i2c.c41 FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
43 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
47 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
/external/u-boot/include/
Dgdsys_fpga.h25 #define FPGA_SET_REG(ix, fld, val) \ macro