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Searched refs:FPR (Results 1 – 25 of 74) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaRegisterInfo.td26 // FPR - One of the 32 64-bit floating-point registers
27 class FPR<bits<5> num, string n> : AlphaReg<n> {
72 def F0 : FPR< 0, "$f0">, DwarfRegNum<[33]>;
73 def F1 : FPR< 1, "$f1">, DwarfRegNum<[34]>;
74 def F2 : FPR< 2, "$f2">, DwarfRegNum<[35]>;
75 def F3 : FPR< 3, "$f3">, DwarfRegNum<[36]>;
76 def F4 : FPR< 4, "$f4">, DwarfRegNum<[37]>;
77 def F5 : FPR< 5, "$f5">, DwarfRegNum<[38]>;
78 def F6 : FPR< 6, "$f6">, DwarfRegNum<[39]>;
79 def F7 : FPR< 7, "$f7">, DwarfRegNum<[40]>;
[all …]
/external/elfutils/backends/
Ds390_corenote.c66 #define FPR(at, n, dwreg) \ macro
71 FPR (1 + 0, 1, 16), /* f0 */
72 FPR (1 + 1, 1, 20), /* f1 */
73 FPR (1 + 2, 1, 17), /* f2 */
74 FPR (1 + 3, 1, 21), /* f3 */
75 FPR (1 + 4, 1, 18), /* f4 */
76 FPR (1 + 5, 1, 22), /* f5 */
77 FPR (1 + 6, 1, 19), /* f6 */
78 FPR (1 + 7, 1, 23), /* f7 */
79 FPR (1 + 8, 1, 24), /* f8 */
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64GenRegisterBankInfo.def17 // 0: FPR 16-bit value.
19 // 1: FPR 32-bit value.
21 // 2: FPR 64-bit value.
23 // 3: FPR 128-bit value.
25 // 4: FPR 256-bit value.
27 // 5: FPR 512-bit value.
42 // 1: FPR 16-bit value. <-- This must match First3OpsIdx.
46 // 4: FPR 32-bit value. <-- This must match First3OpsIdx.
50 // 7: FPR 64-bit value.
54 // 10: FPR 128-bit value.
[all …]
DAArch64RegisterBankInfo.cpp125 CHECK_VALUEMAP(FPR, 16); in AArch64RegisterBankInfo()
126 CHECK_VALUEMAP(FPR, 32); in AArch64RegisterBankInfo()
127 CHECK_VALUEMAP(FPR, 64); in AArch64RegisterBankInfo()
128 CHECK_VALUEMAP(FPR, 128); in AArch64RegisterBankInfo()
129 CHECK_VALUEMAP(FPR, 256); in AArch64RegisterBankInfo()
130 CHECK_VALUEMAP(FPR, 512); in AArch64RegisterBankInfo()
143 CHECK_VALUEMAP_3OPS(FPR, 32); in AArch64RegisterBankInfo()
144 CHECK_VALUEMAP_3OPS(FPR, 64); in AArch64RegisterBankInfo()
145 CHECK_VALUEMAP_3OPS(FPR, 128); in AArch64RegisterBankInfo()
146 CHECK_VALUEMAP_3OPS(FPR, 256); in AArch64RegisterBankInfo()
[all …]
DAArch64RegisterBanks.td17 def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsRegisterInfo.td44 class FPR<bits<5> num, string n> : MipsReg<n> {
142 def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
143 def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>;
144 def F2 : FPR< 2, "F2">, DwarfRegNum<[34]>;
145 def F3 : FPR< 3, "F3">, DwarfRegNum<[35]>;
146 def F4 : FPR< 4, "F4">, DwarfRegNum<[36]>;
147 def F5 : FPR< 5, "F5">, DwarfRegNum<[37]>;
148 def F6 : FPR< 6, "F6">, DwarfRegNum<[38]>;
149 def F7 : FPR< 7, "F7">, DwarfRegNum<[39]>;
150 def F8 : FPR< 8, "F8">, DwarfRegNum<[40]>;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCRegisterInfo.td45 // FPR - One of the 32 64-bit floating-point registers
46 class FPR<bits<5> num, string n> : PPCReg<n> {
136 def F0 : FPR< 0, "f0">, DwarfRegNum<[32, 32]>;
137 def F1 : FPR< 1, "f1">, DwarfRegNum<[33, 33]>;
138 def F2 : FPR< 2, "f2">, DwarfRegNum<[34, 34]>;
139 def F3 : FPR< 3, "f3">, DwarfRegNum<[35, 35]>;
140 def F4 : FPR< 4, "f4">, DwarfRegNum<[36, 36]>;
141 def F5 : FPR< 5, "f5">, DwarfRegNum<[37, 37]>;
142 def F6 : FPR< 6, "f6">, DwarfRegNum<[38, 38]>;
143 def F7 : FPR< 7, "f7">, DwarfRegNum<[39, 39]>;
[all …]
/external/llvm/test/CodeGen/AArch64/GlobalISel/
Darm64-regbankselect.mir78 # FPR is used for both floating point and vector registers.
95 # in FPR, but at the use, it should be GPR.
139 # %1 is forced to be into FPR, but its definition actually
247 # Fast mode maps vector instruction on FPR.
269 ; Now, the default mapping says that %0 and %1 need to be in FPR.
273 ; The mapping of G_OR is on FPR.
294 # Fast mode maps vector instruction on FPR.
300 # is the cheapest, but will need one extra copy to materialize %2 into a FPR.
315 ; Now, the default mapping says that %0 and %1 need to be in FPR.
319 ; The mapping of G_OR is on FPR.
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dvsx-spill.ll92 ; CHECK-P9-REG: lfd [[FPR:[0-9]+]], [[OFF]](1)
93 ; CHECK-P9-REG: xsadddp 1, [[FPR]], [[FPR]]
97 ; CHECK-P9-FISL: lfd [[FPR:[0-9]+]], [[OFF]](1)
98 ; CHECK-P9-FISL: xsadddp 1, [[FPR]], [[FPR]]
Dfastcc_stacksize.ll38 ; No need for Parameter Save Area for calls that utiliizes 8 GPR and 2 FPR.
96 ; Max number of FPR for parameter passing is 13
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Darm64-regbankselect.mir135 # FPR is used for both floating point and vector registers.
154 # in FPR, but at the use, it should be GPR.
194 # %1 is forced to be into FPR, but its definition actually
308 ; Now, the default mapping says that %0 and %1 need to be in FPR.
312 ; The mapping of G_OR is on FPR.
341 ; Now, the default mapping says that %0 and %1 need to be in FPR.
345 ; The mapping of G_OR is on FPR.
350 ; We need to keep %2 into FPR because we do not know anything about it.
734 # %0 has been mapped to GPR, we need to repair to match FPR.
773 # %0 has been mapped to GPR, we need to repair to match FPR.
[all …]
Dselect-neon-vcvtfxu2fp.mir11 # Check that we select a 64-bit FPR vcvtfxu2fp intrinsic into UCVTFd for FPR64.
/external/llvm/lib/Target/SystemZ/
DSystemZMachineFunctionInfo.h52 void setVarArgsFirstFPR(unsigned FPR) { VarArgsFirstFPR = FPR; } in setVarArgsFirstFPR() argument
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZMachineFunctionInfo.h52 void setVarArgsFirstFPR(unsigned FPR) { VarArgsFirstFPR = FPR; } in setVarArgsFirstFPR() argument
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td47 // FPR - One of the 32 64-bit floating-point registers
48 class FPR<bits<5> num, string n> : PPCReg<n> {
53 class QFPR<FPR SubReg, string n> : PPCReg<n> {
76 class VSRL<FPR SubReg, string n> : PPCReg<n> {
115 def F#Index : FPR<Index, "f"#Index>,
126 def QF#Index : QFPR<!cast<FPR>("F"#Index), "q"#Index>,
138 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>,
139 DwarfRegAlias<!cast<FPR>("F"#Index)>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td53 // FPR - One of the 32 64-bit floating-point registers
54 class FPR<bits<5> num, string n> : PPCReg<n> {
59 class QFPR<FPR SubReg, string n> : PPCReg<n> {
82 class VSRL<FPR SubReg, string n> : PPCReg<n> {
118 def F#Index : FPR<Index, "f"#Index>,
132 def QF#Index : QFPR<!cast<FPR>("F"#Index), "q"#Index>,
144 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>,
145 DwarfRegAlias<!cast<FPR>("F"#Index)>;
/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td51 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
157 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
161 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
167 [!cast<FPR>("F"#!shl(I, 1)),
168 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>;
172 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsRegisterInfo.td51 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
157 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
161 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
167 [!cast<FPR>("F"#!shl(I, 1)),
168 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>;
172 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>,
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dasm-10.ll1 ; Test the FPR constraint "f".
Dframe-04.ll68 ; Like f1, but requires one fewer FPR pair. We allocate in numerical order,
121 ; Like f1, but requires only one call-saved FPR pair. We allocate in
/external/llvm/test/CodeGen/SystemZ/
Dasm-10.ll1 ; Test the FPR constraint "f".
Dframe-04.ll68 ; Like f1, but requires one fewer FPR pair. We allocate in numerical order,
121 ; Like f1, but requires only one call-saved FPR pair. We allocate in
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-fixed-point-scalar-cvt-dagcombine.ll5 ; of the value to a GPR and back to and FPR.
/external/llvm/test/CodeGen/AArch64/
Darm64-fixed-point-scalar-cvt-dagcombine.ll5 ; of the value to a GPR and back to and FPR.
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterBank.inc112 RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* Size */ 512, /* Covere…

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