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Searched refs:FPType (Results 1 – 14 of 14) sorted by relevance

/external/v8/src/arm64/
Dassembler-arm64.cc3038 Emit(FPType(vd) | FMOV | Rd(vd) | Rn(vn)); in fmov()
3077 Emit(FPType(vd) | op | Rm(vm) | Rn(vn) | Rd(vd)); in fnmul()
3082 Emit(FPType(fn) | FCMP | Rm(fm) | Rn(fn)); in fcmp()
3091 Emit(FPType(fn) | FCMP_zero | Rn(fn)); in fcmp()
3097 Emit(FPType(fn) | FCCMP | Rm(fm) | Cond(cond) | Rn(fn) | Nzcv(nzcv)); in fccmp()
3104 Emit(FPType(fd) | FCSEL | Rm(fm) | Cond(cond) | Rn(fn) | Rd(fd)); in fcsel()
3109 Emit(SF(rd) | FPType(vn) | op | Rn(vn) | Rd(rd)); in NEONFPConvertToInt()
3221 Emit(SF(rn) | FPType(vd) | SCVTF | Rn(rn) | Rd(vd)); in scvtf()
3223 Emit(SF(rn) | FPType(vd) | SCVTF_fixed | FPScale(64 - fbits) | Rn(rn) | in scvtf()
3231 Emit(SF(rn) | FPType(fd) | UCVTF | Rn(rn) | Rd(fd)); in ucvtf()
[all …]
Dassembler-arm64-inl.h1118 Instr Assembler::FPType(VRegister fd) { return fd.Is64Bits() ? FP64 : FP32; }
Ddisasm-arm64.cc1481 switch (instr->FPType()) { in VisitNEON2RegMisc()
3513 reg_prefix = ((instr->FPType() & 1) == 0) ? 'S' : 'D'; in SubstituteRegisterField()
Dsimulator-arm64.cc3539 switch (instr->FPType()) { in VisitNEON2RegMisc()
4303 if ((instr->FPType() & 1) == 0) { in VisitNEONByIndexedElement()
5181 if ((instr->FPType() & 1) == 0) { in VisitNEONScalarByIndexedElement()
Dconstants-arm64.h207 V_(FPType, 23, 22, Bits) \
Dassembler-arm64.h3150 inline static Instr FPType(VRegister fd);
/external/vixl/src/aarch64/
Dassembler-aarch64.cc2629 Emit(FPType(vd) | FMOV | Rd(vd) | Rn(vn)); in fmov()
2740 Emit(FPType(vd) | op | Rm(vm) | Rn(vn) | Rd(vd)); in fnmul()
2754 Emit(FPType(vn) | op | Rn(vn)); in FPCompareMacro()
2764 Emit(FPType(vn) | op | Rm(vm) | Rn(vn)); in FPCompareMacro()
2804 Emit(FPType(vn) | op | Rm(vm) | Cond(cond) | Rn(vn) | Nzcv(nzcv)); in FPCCompareMacro()
2835 Emit(FPType(vd) | FCSEL | Rm(vm) | Cond(cond) | Rn(vn) | Rd(vd)); in fcsel()
2924 Emit(SF(rd) | FPType(vn) | op | Rn(vn) | Rd(rd)); in NEONFPConvertToInt()
2988 Emit(SF(rd) | FPType(vn) | FCVTZS | Rn(vn) | Rd(rd)); in NEON_FP2REGMISC_FCVT_LIST()
2990 Emit(SF(rd) | FPType(vn) | FCVTZS_fixed | FPScale(64 - fbits) | Rn(vn) | in NEON_FP2REGMISC_FCVT_LIST()
3021 Emit(SF(rd) | FPType(vn) | FCVTZU | Rn(vn) | Rd(rd)); in fcvtzu()
[all …]
Dconstants-aarch64.h106 V_(FPType, 23, 22, ExtractBits) \
Dassembler-aarch64.h3819 static Instr FPType(FPRegister fd) { in FPType() function
/external/swiftshader/third_party/llvm-7.0/llvm/utils/
Dllvm.grm70 FPType ::= float | double | "ppc_fp128" | fp128 | "x86_fp80";
/external/swiftshader/third_party/LLVM/utils/
Dllvm.grm70 FPType ::= float | double | "ppc_fp128" | fp128 | "x86_fp80";
/external/llvm/utils/
Dllvm.grm70 FPType ::= float | double | "ppc_fp128" | fp128 | "x86_fp80";
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/
DInstCombineAddSub.cpp1422 Type *FPType = LHSConv->getType(); in visitFAdd() local
1444 if (IsValidPromotion(FPType, LHSIntVal->getType())) { in visitFAdd()
1461 if (IsValidPromotion(FPType, LHSIntVal->getType())) { in visitFAdd()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp5216 StringRef FPType; in isFPImmLegal() local
5222 FPType = "f64"; in isFPImmLegal()
5225 FPType = "f32"; in isFPImmLegal()
5228 FPType = "f16"; in isFPImmLegal()
5233 LLVM_DEBUG(dbgs() << "Legal " << FPType << " imm value: " << ImmStrVal in isFPImmLegal()
5238 if (!FPType.empty()) in isFPImmLegal()
5239 LLVM_DEBUG(dbgs() << "Illegal " << FPType << " imm value: " << ImmStrVal in isFPImmLegal()