| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 538 FSINCOS, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 571 FSINCOS, enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 161 case ISD::FSINCOS: return "fsincos"; in getOperationName()
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| D | LegalizeDAG.cpp | 2190 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS) in useSinCos()
3154 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) || in ExpandNode()
3158 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0)); in ExpandNode()
3827 case ISD::FSINCOS: in ConvertNodeToLibcall()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 187 case ISD::FSINCOS: return "fsincos"; in getOperationName()
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| D | LegalizeDAG.cpp | 2224 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS) in useSinCos()
3261 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) || in ExpandNode()
3265 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0)); in ExpandNode()
4061 case ISD::FSINCOS: in ConvertNodeToLibcall()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 81 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW, in WebAssemblyTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 88 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, in WebAssemblyTargetLowering()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 155 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in AArch64TargetLowering()
283 setOperationAction(ISD::FSINCOS, MVT::f16, Promote); in AArch64TargetLowering()
329 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand); in AArch64TargetLowering()
361 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand); in AArch64TargetLowering()
403 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in AArch64TargetLowering()
404 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in AArch64TargetLowering()
406 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in AArch64TargetLowering()
407 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in AArch64TargetLowering()
539 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
2402 case ISD::FSINCOS: in LowerOperation()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 222 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in AArch64TargetLowering()
348 setOperationAction(ISD::FSINCOS, MVT::f16, Promote); in AArch64TargetLowering()
349 setOperationAction(ISD::FSINCOS, MVT::v4f16, Promote); in AArch64TargetLowering()
350 setOperationAction(ISD::FSINCOS, MVT::v8f16, Promote); in AArch64TargetLowering()
488 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in AArch64TargetLowering()
489 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in AArch64TargetLowering()
491 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in AArch64TargetLowering()
492 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in AArch64TargetLowering()
637 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
2872 case ISD::FSINCOS: in LowerOperation()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ScheduleAtom.td | 902 def : InstRW<[AtomWrite01_174], (instrs FSINCOS)>;
|
| D | X86InstrFPStack.td | 670 def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>;
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1668 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1673 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1678 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1663 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1668 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1673 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1373 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1428 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrFPStack.td | 585 def FSINCOS : I<0xFB, RawFrm, (outs), (ins), "fsincos", []>, D9;
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1887 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1949 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 766 #define FSINCOS CHOICE(fsincos, fsincos, fsincos) macro
1479 #define FSINCOS fsincos macro
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrFPStack.td | 661 def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", [], IIC_FSINCOS>;
|
| D | X86ISelLowering.cpp | 503 setOperationAction(ISD::FSINCOS, VT, Expand); in X86TargetLowering()
535 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in X86TargetLowering()
547 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in X86TargetLowering()
562 setOperationAction(ISD::FSINCOS, VT, Expand); in X86TargetLowering()
610 setOperationAction(ISD::FSINCOS, MVT::f80, Expand); in X86TargetLowering()
638 setOperationAction(ISD::FSINCOS, VT, Expand); in X86TargetLowering()
1606 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in X86TargetLowering()
1607 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in X86TargetLowering()
21762 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG); in LowerOperation()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 359 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in MipsTargetLowering()
360 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in MipsTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 437 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in MipsTargetLowering()
438 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in MipsTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 5385 {DBGFIELD("FSINCOS") 1, false, false, 74, 1, 60, 1, 0, 0}, // #673
6601 {DBGFIELD("FSINCOS") 1, false, false, 79, 2, 4, 1, 0, 0}, // #673
7817 {DBGFIELD("FSINCOS") 1, false, false, 1, 1, 4, 1, 0, 0}, // #673
9033 {DBGFIELD("FSINCOS") 1, false, false, 79, 2, 4, 1, 0, 0}, // #673
10249 {DBGFIELD("FSINCOS") 1, false, false, 226, 2, 4, 1, 0, 0}, // #673
11465 {DBGFIELD("FSINCOS") 1, false, false, 79, 2, 4, 1, 0, 0}, // #673
12681 {DBGFIELD("FSINCOS") 1, false, false, 3037, 2, 4, 1, 0, 0}, // #673
13897 {DBGFIELD("FSINCOS") 1, false, false, 79, 2, 4, 1, 0, 0}, // #673
15113 {DBGFIELD("FSINCOS") 1, false, false, 0, 0, 4, 1, 0, 0}, // #673
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 938 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in ARMTargetLowering()
939 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in ARMTargetLowering()
981 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in ARMTargetLowering()
982 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in ARMTargetLowering()
7217 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG); in LowerOperation()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1070 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in ARMTargetLowering()
1071 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in ARMTargetLowering()
1105 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in ARMTargetLowering()
1106 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in ARMTargetLowering()
8130 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG); in LowerOperation()
|