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Searched refs:FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/include/
Dfsl_ddr_sdram.h49 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) macro
55 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) macro
66 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ macro
/external/u-boot/drivers/ddr/fsl/
Dctrl_regs.c707 cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR; in set_timing_cfg_2()