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Searched refs:FSL_SRDSCR0_DPP_1V2 (Results 1 – 1 of 1) sorted by relevance

/external/u-boot/arch/powerpc/cpu/mpc83xx/
Dserdes.c18 #define FSL_SRDSCR0_DPP_1V2 0x00008800 macro
54 tmp &= ~FSL_SRDSCR0_DPP_1V2; in fsl_setup_serdes()