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Searched refs:FSL_SRDSCR2_SEIC_SGMII (Results 1 – 1 of 1) sorted by relevance

/external/u-boot/arch/powerpc/cpu/mpc83xx/
Dserdes.c30 #define FSL_SRDSCR2_SEIC_SGMII 0x00000101 macro
132 tmp |= FSL_SRDSCR2_SEIC_SGMII; in fsl_setup_serdes()