| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 1677 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost()
1678 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost()
1679 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost()
1680 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost()
1681 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost()
1682 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ in getIntrinsicInstrCost()
1704 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ in getIntrinsicInstrCost()
1705 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ in getIntrinsicInstrCost()
1706 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ in getIntrinsicInstrCost()
1707 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ in getIntrinsicInstrCost()
[all …]
|
| D | X86.td | 299 // FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
301 // vector FSQRT has higher throughput than the corresponding NR code.
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 450 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
|
| /external/one-true-awk/ |
| D | awk.h | 124 #define FSQRT 2 macro
|
| D | lex.c | 82 { "sqrt", FSQRT, BLTIN },
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 524 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
|
| D | BasicTTIImpl.h | 201 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
742 ISDs.push_back(ISD::FSQRT); in getIntrinsicInstrCost()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 557 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
|
| D | BasicTTIImpl.h | 327 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
1013 ISDs.push_back(ISD::FSQRT);
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrFPU.td | 110 def FSQRT : ArithF2<0x16, 0x380, "fsqrt ", IIC_FPUs>;
135 def : Pat<(fsqrt GPR:$V), (FSQRT GPR:$V)>;
|
| D | MBlazeInstrFormats.td | 27 def FRRC : Format<10>; // SEXT8, SEXT16, SRA, SRC, SRL, FLT, FINT, FSQRT
|
| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 265 X86_INTRINSIC_DATA(avx_sqrt_pd_256, INTR_TYPE_1OP, ISD::FSQRT, 0),
266 X86_INTRINSIC_DATA(avx_sqrt_ps_256, INTR_TYPE_1OP, ISD::FSQRT, 0),
1429 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1430 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1431 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_512, INTR_TYPE_1OP_MASK_RM, ISD::FSQRT,
1433 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1434 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1435 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_512, INTR_TYPE_1OP_MASK_RM, ISD::FSQRT,
1873 X86_INTRINSIC_DATA(sse_sqrt_ps, INTR_TYPE_1OP, ISD::FSQRT, 0),
1923 X86_INTRINSIC_DATA(sse2_sqrt_pd, INTR_TYPE_1OP, ISD::FSQRT, 0),
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 327 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR()
372 Opcode = ISD::FSQRT; break; in mightUseCTR()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 301 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR()
344 Opcode = ISD::FSQRT; break; in mightUseCTR()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 174 case ISD::FSQRT: in LegalizeOp()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 120 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in AlphaTargetLowering()
121 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in AlphaTargetLowering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
| D | MBlazeDisassembler.cpp | 235 case 0x380: return MBlaze::FSQRT; in decodeFADD()
|
| /external/v8/src/ppc/ |
| D | disasm-ppc.cc | 975 case FSQRT: { in DecodeExt4()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 158 case ISD::FSQRT: return "fsqrt"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 103 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
1040 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
1883 case ISD::FSQRT: in PromoteFloatResult()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 547 // FDIV,FSQRT
549 // TODO: Specialize FSQRT for longer latency.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 549 // FDIV,FSQRT
551 // TODO: Specialize FSQRT for longer latency.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 181 case ISD::FSQRT: return "fsqrt"; in getOperationName()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 157 defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrFPU.td | 124 defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
|