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Searched refs:FSUB_D (Results 1 – 14 of 14) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoD.td93 def FSUB_D : FPALUD_rr_frm<0b0000101, "fsub.d">;
94 def : FPALUDDynFrmAlias<FSUB_D, "fsub.d">;
226 def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>;
/external/mesa3d/src/mesa/x86/
Dassyntax.h781 #define FSUB_D(a) CHOICE(fsubl a, fsubl a, fsubd a) macro
1494 #define FSUB_D(a) fsub D_(a) macro
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc808 33572692U, // FSUB_D
2522 0U, // FSUB_D
DMipsGenDisassemblerTables.inc2676 /* 9223 */ MCD_OPC_Decode, 151, 6, 117, // Opcode: FSUB_D
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenMCCodeEmitter.inc1502 UINT64_C(2019557403), // FSUB_D
7303 case Mips::FSUB_D:
9228 Feature_HasStdEnc | Feature_HasMSA | 0, // FSUB_D = 1489
DMipsGenAsmWriter.inc2717 268454178U, // FSUB_D
5348 0U, // FSUB_D
DMipsGenFastISel.inc1667 return fastEmitInst_rr(Mips::FSUB_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenInstrInfo.inc1504 FSUB_D = 1489,
5549 …9, 3, 1, 4, 636, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1489 = FSUB_D
DMipsGenGlobalISel.inc14162 …4] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUB_D:{ *:[v2f64] } MSA1…
14163 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D,
DMipsGenDisassemblerTables.inc5135 /* 11824 */ MCD::OPC_Decode, 209, 11, 253, 1, // Opcode: FSUB_D
DMipsGenAsmMatcher.inc6290 …{ 4758 /* fsub.d */, Mips::FSUB_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Fea…
DMipsGenDAGISel.inc27400 /* 51501*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUB_D), 0,
27403 … // Dst: (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3112 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3119 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;