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Searched refs:FSUB_S (Results 1 – 16 of 16) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoF.td114 def FSUB_S : FPALUS_rr_frm<0b0000100, "fsub.s">;
115 def : FPALUSDynFrmAlias<FSUB_S, "fsub.s">;
266 def : PatFpr32Fpr32DynFrm<fsub, FSUB_S>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsScheduleP5600.td434 FSUB_D32, FSUB_D64, FSUB_S)>;
DMipsInstrFPU.td612 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
/external/llvm/lib/Target/Mips/
DMipsInstrFPU.td477 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
/external/mesa3d/src/mesa/x86/
Dassyntax.h780 #define FSUB_S(a) CHOICE(fsubs a, fsubs a, fsubs a) macro
1493 #define FSUB_S(a) fsub S_(a) macro
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc885 {DBGFIELD("FSUB_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #610
1905 {DBGFIELD("FSUB_S") 1, false, false, 58, 2, 6, 1, 0, 0}, // #610
DMipsGenMCCodeEmitter.inc1507 UINT64_C(1174405121), // FSUB_S
3263 case Mips::FSUB_S: {
9233 Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FSUB_S = 1494
DMipsGenInstrInfo.inc1509 FSUB_S = 1494,
3267 FSUB_S = 610,
5554 …, 3, 1, 4, 610, 0, 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1494 = FSUB_S
10141 { Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM },
DMipsGenAsmWriter.inc2722 268458767U, // FSUB_S
5353 0U, // FSUB_S
DMipsGenFastISel.inc1631 return fastEmitInst_rr(Mips::FSUB_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenGlobalISel.inc14003 …// (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] …
14004 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S,
DMipsGenDisassemblerTables.inc3312 /* 2637 */ MCD::OPC_Decode, 214, 11, 204, 1, // Opcode: FSUB_S
DMipsGenAsmMatcher.inc7422 …{ 8784 /* sub.s */, Mips::FSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature…
DMipsGenDAGISel.inc27327 /* 51366*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUB_S), 0,
27330 … // Dst: (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc812 33576978U, // FSUB_S
2526 0U, // FSUB_S
DMipsGenDisassemblerTables.inc855 /* 1805 */ MCD_OPC_Decode, 155, 6, 70, // Opcode: FSUB_S