| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 1623 X86_INTRINSIC_DATA(avx512_mask_xor_pd_128, INTR_TYPE_2OP_MASK, X86ISD::FXOR, 0),
1624 X86_INTRINSIC_DATA(avx512_mask_xor_pd_256, INTR_TYPE_2OP_MASK, X86ISD::FXOR, 0),
1625 X86_INTRINSIC_DATA(avx512_mask_xor_pd_512, INTR_TYPE_2OP_MASK, X86ISD::FXOR, 0),
1626 X86_INTRINSIC_DATA(avx512_mask_xor_ps_128, INTR_TYPE_2OP_MASK, X86ISD::FXOR, 0),
1627 X86_INTRINSIC_DATA(avx512_mask_xor_ps_256, INTR_TYPE_2OP_MASK, X86ISD::FXOR, 0),
1628 X86_INTRINSIC_DATA(avx512_mask_xor_ps_512, INTR_TYPE_2OP_MASK, X86ISD::FXOR, 0),
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| D | X86ISelLowering.h | 53 FXOR, enumerator
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| D | X86InstrFragmentsSIMD.td | 57 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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| D | X86ISelLowering.cpp | 14362 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR; in LowerFABSorFNEG()
22085 case X86ISD::FXOR: return "X86ISD::FXOR"; in getTargetNodeName()
26278 case ISD::XOR: FPOpcode = X86ISD::FXOR; break; in combineBitcast()
28176 FPOpcode = X86ISD::FXOR; in convertIntLogicToFPLogic()
29792 case X86ISD::FXOR: IntOpcode = ISD::XOR; break; in lowerX86FPLogicOp()
29804 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); in combineFOr()
30976 case X86ISD::FXOR: in PerformDAGCombine()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrVIS.td | 106 def FXOR : VISInst<0b001101100, "fxor">;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrVIS.td | 106 def FXOR : VISInst<0b001101100, "fxor">;
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.h | 54 FXOR, enumerator
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| D | X86InstrFragmentsSIMD.td | 47 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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| D | X86ISelLowering.cpp | 8061 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); in LowerFNEG()
10627 case X86ISD::FXOR: return "X86ISD::FXOR"; in getTargetNodeName()
13980 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); in PerformFORCombine()
14217 case X86ISD::FXOR: in PerformDAGCombine()
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| D | X86GenFastISel.inc | 2823 // FastEmit functions for X86ISD::FXOR.
3692 case X86ISD::FXOR: return FastEmit_X86ISD_FXOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
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| D | X86GenDAGISel.inc | 39438 /*SwitchOpcode*/ 23|128,2/*279*/, TARGET_VAL(X86ISD::FXOR),// ->82518
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 53 FXOR, enumerator
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| D | X86InstrFragmentsSIMD.td | 54 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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| D | X86ISelLowering.cpp | 17463 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR; in LowerFABSorFNEG()
25903 case X86ISD::FXOR: return "X86ISD::FXOR"; in getTargetNodeName()
31779 case ISD::XOR: FPOpcode = X86ISD::FXOR; break; in combineBitcast()
34589 FPOpcode = X86ISD::FXOR; in convertIntLogicToFPLogic()
36963 if (Op.getOpcode() != X86ISD::FXOR && Op.getOpcode() != ISD::XOR) in isFNEG()
37047 case X86ISD::FXOR: IntOpcode = ISD::XOR; break; in lowerX86FPLogicOp()
37081 MVT::v4i32, DAG.getNode(X86ISD::FXOR, SDLoc(N), MVT::v4f32, in combineXor()
37182 if (N0.getOpcode() == X86ISD::FXOR && isAllOnesConstantFP(N0.getOperand(1))) in combineFAndFNotToFAndn()
37186 if (N1.getOpcode() == X86ISD::FXOR && isAllOnesConstantFP(N1.getOperand(1))) in combineFAndFNotToFAndn()
37226 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); in combineFOr()
[all …]
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| /external/capstone/arch/Sparc/ |
| D | SparcGenDisassemblerTables.inc | 1127 /* 4500 */ MCD_OPC_Decode, 163, 2, 27, // Opcode: FXOR
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| D | SparcGenAsmWriter.inc | 312 5526U, // FXOR
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenFastISel.inc | 9457 // FastEmit functions for X86ISD::FXOR.
12005 case X86ISD::FXOR: return fastEmit_X86ISD_FXOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
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