| /external/v8/src/wasm/baseline/arm64/ |
| D | liftoff-assembler-arm64.h | 724 Fcvt(dst.fp().S(), src.fp().D()); in emit_type_conversion()
742 Fcvt(dst.fp().D(), src.fp().S()); in emit_type_conversion()
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 13173 __ Fcvt(d0, s16); in TEST() local
13174 __ Fcvt(d1, s17); in TEST() local
13175 __ Fcvt(d2, s18); in TEST() local
13176 __ Fcvt(d3, s19); in TEST() local
13177 __ Fcvt(d4, s20); in TEST() local
13178 __ Fcvt(d5, s21); in TEST() local
13179 __ Fcvt(d6, s22); in TEST() local
13180 __ Fcvt(d7, s23); in TEST() local
13181 __ Fcvt(d8, s24); in TEST() local
13182 __ Fcvt(d9, s25); in TEST() local
[all …]
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| D | test-simulator-aarch64.cc | 5000 __ Fcvt(input_1.D(), input_1); in GenerateSum() local
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| /external/v8/src/arm64/ |
| D | macro-assembler-arm64-inl.h | 524 void TurboAssembler::Fcvt(const VRegister& fd, const VRegister& fn) { in Fcvt() function
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| D | macro-assembler-arm64.h | 1007 inline void Fcvt(const VRegister& fd, const VRegister& fn);
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| D | macro-assembler-arm64.cc | 3080 Fcvt(pcs[i].VReg(), args[i].VReg()); in PrintfNoPreserve()
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 1395 __ Fcvt(i.OutputDoubleRegister(), i.InputDoubleRegister(0).S()); in AssembleArchInstruction() local
1398 __ Fcvt(i.OutputDoubleRegister().S(), i.InputDoubleRegister(0)); in AssembleArchInstruction() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2589 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); in ExpandLegalINT_TO_FP() local
2592 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); in ExpandLegalINT_TO_FP()
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 2538 Fcvt(FPRegister(pcs[i]), FPRegister(args[i])); in PrintfNoPreserve()
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| D | macro-assembler-aarch64.h | 1365 void Fcvt(const VRegister& vd, const VRegister& vn) { in Fcvt() function
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2407 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); in ExpandLegalINT_TO_FP() local
2411 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); in ExpandLegalINT_TO_FP()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2441 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); in ExpandLegalINT_TO_FP() local
2445 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); in ExpandLegalINT_TO_FP()
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