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Searched refs:GICC_BASE (Results 1 – 18 of 18) sorted by relevance

/external/u-boot/arch/arm/cpu/armv7/sunxi/
Dpsci.c27 #define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15) macro
224 reg = readl(GICC_BASE + GICC_IAR); in psci_fiq_enter()
231 writel(reg, GICC_BASE + GICC_EOIR); in psci_fiq_enter()
303 writel(0xff, GICC_BASE + GICC_PMR); in psci_arch_init()
306 setbits_le32(GICC_BASE + GICC_CTLR, BIT(3)); in psci_arch_init()
/external/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
Dconfig.h220 #define GICC_BASE 0x01402000 macro
248 #define GICC_BASE 0x01402000 macro
278 #define GICC_BASE 0x01420000 macro
/external/u-boot/arch/arm/mach-rmobile/
Dlowlevel_init_gen3.S41 ldr x1, =GICC_BASE
55 ldr x0, =GICC_BASE
/external/u-boot/include/configs/
Dvexpress_aemv8a.h90 #define GICC_BASE (0x2c000000) macro
93 #define GICC_BASE (0x2C02f000) macro
Dsun50i.h21 #define GICC_BASE 0x1c82000 macro
Dhikey.h44 #define GICC_BASE 0xf6802000 macro
Drcar-gen3-common.h30 #define GICC_BASE 0xF1020000 macro
Dmeson-gx-common.h24 #define GICC_BASE 0xc4302000 macro
Ds32v234evb.h18 #define GICC_BASE 0x7D002000 macro
Dxilinx_zynqmp.h20 #define GICC_BASE 0xF9020000 macro
/external/u-boot/arch/arm/include/asm/arch-tegra186/
Dtegra.h10 #define GICC_BASE 0x03882000 /* Generic Int Cntrlr CPU I/F */ macro
/external/u-boot/arch/arm/include/asm/arch-tegra210/
Dtegra.h11 #define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */ macro
/external/u-boot/arch/arm/mach-socfpga/include/mach/
Dbase_addr_s10.h41 #define GICC_BASE 0xfffc2000 macro
/external/u-boot/arch/arm/mach-snapdragon/include/mach/
Dsysmap-apq8016.h11 #define GICC_BASE (0x0a20c000) macro
/external/u-boot/arch/arm/cpu/armv8/
Dstart.S293 ldr x1, =GICC_BASE
308 ldr x0, =GICC_BASE
/external/u-boot/arch/arm/lib/
Dgic_64.S55 ldr x1, =GICC_BASE /* GICC_CTLR */
/external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
Dfdt.c205 reg[2] = cpu_to_fdt64(GICC_BASE); in fdt_fixup_gic()
Dlowlevel.S33 ldr x1, =GICC_BASE