Searched refs:GICC_BASE (Results 1 – 18 of 18) sorted by relevance
27 #define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15) macro224 reg = readl(GICC_BASE + GICC_IAR); in psci_fiq_enter()231 writel(reg, GICC_BASE + GICC_EOIR); in psci_fiq_enter()303 writel(0xff, GICC_BASE + GICC_PMR); in psci_arch_init()306 setbits_le32(GICC_BASE + GICC_CTLR, BIT(3)); in psci_arch_init()
220 #define GICC_BASE 0x01402000 macro248 #define GICC_BASE 0x01402000 macro278 #define GICC_BASE 0x01420000 macro
41 ldr x1, =GICC_BASE55 ldr x0, =GICC_BASE
90 #define GICC_BASE (0x2c000000) macro93 #define GICC_BASE (0x2C02f000) macro
21 #define GICC_BASE 0x1c82000 macro
44 #define GICC_BASE 0xf6802000 macro
30 #define GICC_BASE 0xF1020000 macro
24 #define GICC_BASE 0xc4302000 macro
18 #define GICC_BASE 0x7D002000 macro
20 #define GICC_BASE 0xF9020000 macro
10 #define GICC_BASE 0x03882000 /* Generic Int Cntrlr CPU I/F */ macro
11 #define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */ macro
41 #define GICC_BASE 0xfffc2000 macro
11 #define GICC_BASE (0x0a20c000) macro
293 ldr x1, =GICC_BASE308 ldr x0, =GICC_BASE
55 ldr x1, =GICC_BASE /* GICC_CTLR */
205 reg[2] = cpu_to_fdt64(GICC_BASE); in fdt_fixup_gic()
33 ldr x1, =GICC_BASE