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Searched refs:GPC_IPS_BASE_ADDR (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-imx/mx7/
Dpsci-mx7.c39 writel(enable, GPC_IPS_BASE_ADDR + offset); in imx_gpcv2_set_m_core_pgc()
49 val = readl(GPC_IPS_BASE_ADDR + reg); in imx_gpcv2_set_core1_power()
51 writel(val, GPC_IPS_BASE_ADDR + reg); in imx_gpcv2_set_core1_power()
53 while ((readl(GPC_IPS_BASE_ADDR + reg) & in imx_gpcv2_set_core1_power()
/external/u-boot/arch/arm/include/asm/arch-mx7/
Dimx-regs.h116 #define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000) macro