| /external/u-boot/drivers/clk/rockchip/ |
| D | clk_rk3036.c | 42 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
119 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
120 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
122 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; in rkclk_init()
123 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
125 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
126 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
142 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
143 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
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| D | clk_rk3328.c | 37 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
290 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; in rkclk_init()
355 return DIV_TO_RATE(GPLL_HZ, div); in rk3328_i2c_get_clk()
362 src_clk_div = GPLL_HZ / hz; in rk3328_i2c_set_clk()
399 return DIV_TO_RATE(GPLL_HZ, src_clk_div); in rk3328_i2c_set_clk()
423 pll_rate = GPLL_HZ; in rk3328_gmac2io_set_clk()
463 return DIV_TO_RATE(GPLL_HZ, div) / 2; in rk3328_mmc_get_clk()
486 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); in rk3328_mmc_set_clk()
512 return DIV_TO_RATE(GPLL_HZ, div); in rk3328_pwm_get_clk()
517 u32 div = GPLL_HZ / hz; in rk3328_pwm_set_clk()
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| D | clk_rk3399.c | 50 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
489 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_i2c_get_clk()
497 src_clk_div = GPLL_HZ / hz; in rk3399_i2c_set_clk()
588 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_spi_get_clk()
596 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rk3399_spi_set_clk()
686 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_mmc_get_clk()
700 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); in rk3399_mmc_set_clk()
719 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); in rk3399_mmc_set_clk()
728 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); in rk3399_mmc_set_clk()
1044 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; in rkclk_init()
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| D | clk_rk322x.c | 39 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
120 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
121 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
124 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); in rkclk_init()
127 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
143 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
144 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
256 pll_rate = GPLL_HZ; in rk322x_mac_set_clk()
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| D | clk_rk3128.c | 36 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
181 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
182 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
204 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
205 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
421 src_clk_div = GPLL_HZ / hz; in rk3128_vop_set_clk()
463 parent = GPLL_HZ; in rk3128_vop_get_rate()
468 parent = GPLL_HZ; in rk3128_vop_get_rate()
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| D | clk_rk3368.c | 38 #define GPLL_HZ (576 * 1000 * 1000) macro
53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
211 { .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ }, in rk3368_mmc_find_best_rate_and_parent()
330 pll_rate = GPLL_HZ; in rk3368_gmac_set_clk()
397 return DIV_TO_RATE(GPLL_HZ, div); in rk3368_spi_get_clk()
405 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); in rk3368_spi_set_clk()
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| D | clk_rk3188.c | 81 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
399 aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1; in rkclk_init()
400 assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
427 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
428 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
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| D | clk_rk3288.c | 140 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
315 pll_rate = GPLL_HZ; in rockchip_mac_set_clk()
402 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; in rkclk_init()
403 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
424 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
425 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | cru_rk3328.h | 51 #define GPLL_HZ (576 * MHz) macro
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| D | cru_rv1108.h | 14 #define GPLL_HZ (594 * 1000000) macro
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| D | cru_rk3188.h | 12 #define GPLL_HZ (594 * 1000000) macro
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| D | cru_rk3399.h | 73 #define GPLL_HZ (594*MHz) macro
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| D | cru_rk3036.h | 13 #define GPLL_HZ (594 * 1000000) macro
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| D | cru_rk322x.h | 14 #define GPLL_HZ (594 * MHz) macro
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| D | cru_rk3128.h | 15 #define GPLL_HZ (594 * MHz) macro
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| D | cru_rk3288.h | 14 #define GPLL_HZ (594 * 1000000) macro
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