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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeInstrFPU.td22 TA<op, 0x000, (outs GPR:$dst), (ins memrr:$addr),
24 [(set (f32 GPR:$dst), (OpNode xaddr:$addr))], IIC_MEMl>;
27 TB<op, (outs GPR:$dst), (ins memri:$addr),
29 [(set (f32 GPR:$dst), (OpNode iaddr:$addr))], IIC_MEMl>;
32 TA<op, 0x000, (outs), (ins GPR:$dst, memrr:$addr),
34 [(OpNode (f32 GPR:$dst), xaddr:$addr)], IIC_MEMs>;
37 TB<op, (outs), (ins GPR:$dst, memrr:$addr),
39 [(OpNode (f32 GPR:$dst), iaddr:$addr)], IIC_MEMs>;
43 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
45 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
[all …]
DMBlazeInstrInfo.td103 let MIOperandInfo = (ops GPR, simm16);
109 let MIOperandInfo = (ops GPR, GPR);
165 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
167 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
171 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
173 [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIC_ALU>;
176 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
182 SHT<op, flags, (outs GPR:$dst), (ins GPR:$b, Od:$c),
184 [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIC_SHT>;
188 TAR<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrInfo.td268 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
468 let MIOperandInfo = (ops GPR, i32imm);
478 let MIOperandInfo = (ops GPR, GPR, i32imm);
488 let MIOperandInfo = (ops GPR, i32imm);
622 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
634 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
673 let MIOperandInfo = (ops GPR, i32imm);
688 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
702 let MIOperandInfo = (ops GPR, i32imm);
705 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrInfo.td417 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
650 let MIOperandInfo = (ops GPR, i32imm);
661 let MIOperandInfo = (ops GPR, GPR, i32imm);
672 let MIOperandInfo = (ops GPR, i32imm);
946 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
967 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
1023 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
1024 // the GPR is purely vestigal at this point.
1045 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
1070 let MIOperandInfo = (ops GPR, i32imm);
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td193 let MIOperandInfo = (ops GPR:$base, i32lo16s:$offset, AluOp:$Opcode);
205 let MIOperandInfo = (ops GPR:$Op1, GPR:$Op2, AluOp:$Opcode);
227 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
278 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
282 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
294 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
296 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
303 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
307 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
[all …]
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td195 let MIOperandInfo = (ops GPR:$base, i32lo16s:$offset, AluOp:$Opcode);
207 let MIOperandInfo = (ops GPR:$Op1, GPR:$Op2, AluOp:$Opcode);
229 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
280 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
284 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
296 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
298 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
304 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
305 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
309 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td220 (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
228 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
237 (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
242 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
247 : RVInstIShift<arithshift, funct3, OPC_OP_IMM, (outs GPR:$rd),
248 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
253 : RVInstR<funct7, funct3, OPC_OP, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
258 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins uimm12:$imm12, GPR:$rs1),
263 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd),
269 : RVInstIShiftW<arithshift, funct3, OPC_OP_IMM_32, (outs GPR:$rd),
[all …]
DRISCVInstrInfoF.td82 : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd),
92 (ins GPR:$rs1, simm12:$imm12),
100 (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12),
132 def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s"> {
135 def : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>;
137 def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s"> {
140 def : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>;
142 def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w"> {
150 def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s"> {
154 def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w"> {
[all …]
DRISCVInstrInfoD.td60 : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
71 (ins GPR:$rs1, simm12:$imm12),
79 (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12),
124 def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d"> {
128 def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d"> {
131 def : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>;
133 def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d"> {
136 def : FPUnaryOpDynFrmAlias<FCVT_WU_D, "fcvt.wu.d", GPR, FPR64>;
138 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w"> {
142 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu"> {
[all …]
DRISCVInstrInfoA.td22 (outs GPR:$rd), (ins GPR:$rs1),
37 (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
94 defm : StPat<atomic_store_8, SB, GPR>;
95 defm : StPat<atomic_store_16, SH, GPR>;
96 defm : StPat<atomic_store_32, SW, GPR>;
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaRegisterInfo.td21 // GPR - One of the 32 32-bit general-purpose registers
22 class GPR<bits<5> num, string n> : AlphaReg<n> {
38 def R0 : GPR< 0, "$0">, DwarfRegNum<[0]>;
39 def R1 : GPR< 1, "$1">, DwarfRegNum<[1]>;
40 def R2 : GPR< 2, "$2">, DwarfRegNum<[2]>;
41 def R3 : GPR< 3, "$3">, DwarfRegNum<[3]>;
42 def R4 : GPR< 4, "$4">, DwarfRegNum<[4]>;
43 def R5 : GPR< 5, "$5">, DwarfRegNum<[5]>;
44 def R6 : GPR< 6, "$6">, DwarfRegNum<[6]>;
45 def R7 : GPR< 7, "$7">, DwarfRegNum<[7]>;
[all …]
/external/llvm/test/CodeGen/Mips/
Dfpbr.ll3 …s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
6 ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
16 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
17 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
18 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
20 ; GPR: not $[[GPRCC]], $[[GPRCC]]
21 ; 32-GPR: bnez $[[GPRCC]], $BB0_2
22 ; 64-GPR: bnezc $[[GPRCC]], $BB0_2
51 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
52 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
[all …]
Danalyzebranch.ll3 ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
7 ; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
16 ; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]]
17 ; 32-GPR: mthc1 $zero, $[[Z:f[0-9]]]
18 ; 64-GPR: dmtc1 $zero, $[[Z:f[0-9]]]
19 ; GPR: cmp.lt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12
20 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
21 ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
22 ; GPR: bnezc $[[GPRCC]], $BB
49 ; GPR: mtc1 $zero, $[[Z:f[0-9]]]
[all …]
Dmips64muldiv.ll4 ; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR
9 ; GPR - Targets with register based mul/div (i.e. MIPS32r6)
16 ; GPR: dmul $2, ${{[45]}}, ${{[45]}}
33 ; GPR: dmuh $[[T1:[0-9]+]], $4, $[[T0]]
46 ; GPR: ddivu $2, $4, $5
56 ; GPR: ddiv $2, $4, $5
66 ; GPR: dmodu $2, $4, $5
76 ; GPR: dmod $2, $4, $5
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td360 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
561 let MIOperandInfo = (ops GPR, i32imm);
572 let MIOperandInfo = (ops GPR, GPR, i32imm);
583 let MIOperandInfo = (ops GPR, i32imm);
827 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
848 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
902 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
919 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
920 // the GPR is purely vestigal at this point.
941 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dvertex-fetch-encoding.ll6 ; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[G…
7 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[GPR]],0x00,0x0[[G…
26 ; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #3 ; encoding: [0x40,0x03,0x0[[GPR]],0x10,0x0[[G…
27 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #3 ; encoding: [0x40,0x03,0x0[[GPR]],0x00,0x0[[G…
36 ; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #2 ; encoding: [0x40,0x02,0x0[[GPR]],0x10,0x0[[G…
37 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #2 ; encoding: [0x40,0x02,0x0[[GPR]],0x00,0x0[[G…
Dliterals.ll39 ; CHECK: MOV {{\** *}}T[[GPR:[0-9]]].X, 0.0
40 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Y, 0.0
41 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Z, 0.0
42 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].W, 0.0
51 ; CHECK: DOT4 T[[GPR:[0-9]]].X, 1.0
52 ; CHECK-NEXT: DOT4 T[[GPR]].Y (MASKED), 1.0
53 ; CHECK-NEXT: DOT4 T[[GPR]].Z (MASKED), 1.0
54 ; CHECK-NEXT: DOT4 * T[[GPR]].W (MASKED), 1.0
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dfpbr.ll3 …s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
6 ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
17 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
18 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
19 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
21 ; GPR: not $[[GPRCC]], $[[GPRCC]]
22 ; 32-GPR: bnez $[[GPRCC]], $BB0_2
23 ; 64-GPR: bnezc $[[GPRCC]], .LBB0_2
53 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
54 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
[all …]
Dmips64muldiv.ll4 ; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR
9 ; GPR - Targets with register based mul/div (i.e. MIPS32r6)
16 ; GPR: dmul $2, ${{[45]}}, ${{[45]}}
33 ; GPR: dmuh $[[T1:[0-9]+]], $4, $[[T0]]
46 ; GPR: ddivu $2, $4, $5
56 ; GPR: ddiv $2, $4, $5
66 ; GPR: dmodu $2, $4, $5
76 ; GPR: dmod $2, $4, $5
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/
DBPFInstrInfo.td81 let MIOperandInfo = (ops GPR, i16imm);
141 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
157 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
214 (outs GPR:$dst),
215 (ins GPR:$src2, GPR:$src),
217 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
219 (outs GPR:$dst),
220 (ins GPR:$src2, i64imm:$imm),
222 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>;
260 def NEG_64: NEG_RR<BPF_ALU64, BPF_NEG, (outs GPR:$dst), (ins GPR:$src),
[all …]
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.td64 let MIOperandInfo = (ops GPR, i16imm);
83 : InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
104 : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
141 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, i64imm:$imm),
143 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
160 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, GPR:$src),
162 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
199 : InstBPF<(outs GPR:$dst), (ins GPR:$src),
218 : InstBPF<(outs GPR:$dst), (ins i64imm:$imm),
220 [(set GPR:$dst, (i64 i64immSExt32:$imm))]> {
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCRegisterInfo.td28 // GPR - One of the 32 32-bit general-purpose registers
29 class GPR<bits<5> num, string n> : PPCReg<n> {
34 class GP8<GPR SubReg, string n> : PPCReg<n> {
68 def R0 : GPR< 0, "r0">, DwarfRegNum<[-2, 0]>;
69 def R1 : GPR< 1, "r1">, DwarfRegNum<[-2, 1]>;
70 def R2 : GPR< 2, "r2">, DwarfRegNum<[-2, 2]>;
71 def R3 : GPR< 3, "r3">, DwarfRegNum<[-2, 3]>;
72 def R4 : GPR< 4, "r4">, DwarfRegNum<[-2, 4]>;
73 def R5 : GPR< 5, "r5">, DwarfRegNum<[-2, 5]>;
74 def R6 : GPR< 6, "r6">, DwarfRegNum<[-2, 6]>;
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dvertex-fetch-encoding.ll5 ; NI: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]]…
7 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x00,0x0[[GPR]]…
Dliterals.ll39 ; CHECK: MOV {{\** *}}T[[GPR:[0-9]]].X, 0.0
40 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Y, 0.0
41 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Z, 0.0
42 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].W, 0.0
51 ; CHECK: DOT4 T[[GPR:[0-9]]].X, 1.0
52 ; CHECK-NEXT: DOT4 T[[GPR]].Y (MASKED), 1.0
53 ; CHECK-NEXT: DOT4 T[[GPR]].Z (MASKED), 1.0
54 ; CHECK-NEXT: DOT4 * T[[GPR]].W (MASKED), 1.0
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64GenRegisterBankInfo.def29 // 6: GPR 32-bit value.
31 // 7: GPR 64-bit value.
66 // 19: GPR 32-bit value.
70 // 22: GPR 64-bit value. <-- This must match Last3OpsIdx.
75 // 25: FPR 16-bit value to GPR 16-bit. <-- This must match
80 // 27: FPR 32-bit value to GPR 32-bit value.
83 // 29: FPR 64-bit value to GPR 64-bit value.
86 // 31: FPR 128-bit value to GPR 128-bit value (invalid)
89 // 33: FPR 256-bit value to GPR 256-bit value (invalid)
92 // 35: FPR 512-bit value to GPR 512-bit value (invalid)
[all …]

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