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Searched refs:GPSR0 (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/sh/include/asm/
Dcpu_sh7734.h46 #define GPSR0 (0xFFFC0004) macro
47 #define GPSR1 (GPSR0 + 0x4)
48 #define GPSR2 (GPSR0 + 0x8)
49 #define GPSR3 (GPSR0 + 0xC)
50 #define GPSR4 (GPSR0 + 0x10)
51 #define GPSR5 (GPSR0 + 0x14)
/external/u-boot/board/zipitz2/
Dzipitz2.c139 writel((1 << 13), GPSR0); in zipitz2_spi_sda()
150 writel((1 << 22), GPSR0); in zipitz2_spi_scl()
194 writel((1 << 19), GPSR0); in lcd_start()
198 writel((1 << 19), GPSR0); in lcd_start()
217 writel((1 << 11), GPSR0); in lcd_start()
/external/u-boot/arch/arm/cpu/pxa/
Dpxa2xx.c181 writel(CONFIG_SYS_GPSR0_VAL, GPSR0); in pxa_gpio_setup()
/external/u-boot/arch/arm/include/asm/arch-pxa/
Dpxa-regs.h1166 #define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO<31:0> */ macro