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Searched refs:HADD (Results 1 – 12 of 12) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h334 X86_INTRINSIC_DATA(avx2_phadd_d, INTR_TYPE_2OP, X86ISD::HADD, 0),
335 X86_INTRINSIC_DATA(avx2_phadd_w, INTR_TYPE_2OP, X86ISD::HADD, 0),
1237 X86_INTRINSIC_DATA(ssse3_phadd_d_128, INTR_TYPE_2OP, X86ISD::HADD, 0),
1238 X86_INTRINSIC_DATA(ssse3_phadd_w_128, INTR_TYPE_2OP, X86ISD::HADD, 0),
DX86ScheduleZnver1.td1100 // HADD, HSUB PS/PD
1447 // HADD, HSUB PS/PD
DX86ISelLowering.h241 HADD, enumerator
DX86InstrFragmentsSIMD.td61 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
DX86ISelLowering.cpp7833 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1); in LowerToHorizontalOp()
7867 X86Opcode = X86ISD::HADD; in LowerToHorizontalOp()
7900 X86Opcode = X86ISD::HADD; in LowerToHorizontalOp()
25949 case X86ISD::HADD: return "X86ISD::HADD"; in getTargetNodeName()
30637 (Opcode0 == X86ISD::FHADD || Opcode0 == X86ISD::HADD || in combineTargetShuffle()
31138 if (HOp.getOpcode() != X86ISD::HADD && HOp.getOpcode() != X86ISD::FHADD && in foldShuffleOfHorizOp()
39111 return DAG.getNode(X86ISD::HADD, DL, Ops[0].getValueType(), Ops); in combineAdd()
/external/llvm/lib/Target/X86/
DX86ISelLowering.h230 HADD, enumerator
DX86IntrinsicsInfo.h287 X86_INTRINSIC_DATA(avx2_phadd_d, INTR_TYPE_2OP, X86ISD::HADD, 0),
288 X86_INTRINSIC_DATA(avx2_phadd_w, INTR_TYPE_2OP, X86ISD::HADD, 0),
1942 X86_INTRINSIC_DATA(ssse3_phadd_d_128, INTR_TYPE_2OP, X86ISD::HADD, 0),
1943 X86_INTRINSIC_DATA(ssse3_phadd_w_128, INTR_TYPE_2OP, X86ISD::HADD, 0),
DX86InstrFragmentsSIMD.td67 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
DX86SchedHaswell.td1872 // HADD, HSUB PS/PD
DX86ISelLowering.cpp6403 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1); in LowerToHorizontalOp()
6437 X86Opcode = X86ISD::HADD; in LowerToHorizontalOp()
6470 X86Opcode = X86ISD::HADD; in LowerToHorizontalOp()
22131 case X86ISD::HADD: return "X86ISD::HADD"; in getTargetNodeName()
30778 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1); in combineAdd()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td666 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v2i32|v4i16|v8i8)(_v.…
730 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v16i8|v2i64|v4i32|v8i…
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc9519 // FastEmit functions for X86ISD::HADD.
12007 case X86ISD::HADD: return fastEmit_X86ISD_HADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);