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Searched refs:HHI_MPLL_CNTL9 (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/drivers/clk/
Dclk_meson.c121 MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
219 {HHI_MPLL_CNTL9, 0, 14}, /* psdm */
220 {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
/external/u-boot/arch/arm/include/asm/arch-meson/
Dclock.h82 #define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ macro