| /external/pcre/dist2/src/sljit/ |
| D | sljitNativePPC_common.c | 136 #define HI(opcode) ((opcode) << 26) macro
139 #define ADD (HI(31) | LO(266))
140 #define ADDC (HI(31) | LO(10))
141 #define ADDE (HI(31) | LO(138))
142 #define ADDI (HI(14))
143 #define ADDIC (HI(13))
144 #define ADDIS (HI(15))
145 #define ADDME (HI(31) | LO(234))
146 #define AND (HI(31) | LO(28))
147 #define ANDI (HI(28))
[all …]
|
| D | sljitNativeMIPS_common.c | 103 #define HI(opcode) ((opcode) << 26) macro
109 #define ABS_S (HI(17) | FMT_S | LO(5))
110 #define ADD_S (HI(17) | FMT_S | LO(0))
111 #define ADDIU (HI(9))
112 #define ADDU (HI(0) | LO(33))
113 #define AND (HI(0) | LO(36))
114 #define ANDI (HI(12))
115 #define B (HI(4))
116 #define BAL (HI(1) | (17 << 16))
117 #define BC1F (HI(17) | (8 << 21))
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | nontemporal.ll | 16 ; CHECK-NEXT: mov d[[HI:[0-9]+]], v0[1]
17 ; CHECK-NEXT: stnp d0, d[[HI]], [x0]
25 ; CHECK-NEXT: mov d[[HI:[0-9]+]], v0[1]
26 ; CHECK-NEXT: stnp d0, d[[HI]], [x0]
34 ; CHECK-NEXT: mov d[[HI:[0-9]+]], v0[1]
35 ; CHECK-NEXT: stnp d0, d[[HI]], [x0]
43 ; CHECK-NEXT: mov s[[HI:[0-9]+]], v0[1]
44 ; CHECK-NEXT: stnp s0, s[[HI]], [x0]
52 ; CHECK-NEXT: mov s[[HI:[0-9]+]], v0[1]
53 ; CHECK-NEXT: stnp s0, s[[HI]], [x0]
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | nontemporal.ll | 16 ; CHECK-NEXT: mov d[[HI:[0-9]+]], v0[1]
17 ; CHECK-NEXT: stnp d0, d[[HI]], [x0]
25 ; CHECK-NEXT: mov d[[HI:[0-9]+]], v0[1]
26 ; CHECK-NEXT: stnp d0, d[[HI]], [x0]
34 ; CHECK-NEXT: mov d[[HI:[0-9]+]], v0[1]
35 ; CHECK-NEXT: stnp d0, d[[HI]], [x0]
43 ; CHECK-NEXT: mov s[[HI:[0-9]+]], v0[1]
44 ; CHECK-NEXT: stnp s0, s[[HI]], [x0]
52 ; CHECK-NEXT: mov s[[HI:[0-9]+]], v0[1]
53 ; CHECK-NEXT: stnp s0, s[[HI]], [x0]
[all …]
|
| D | mul-lohi.ll | 6 ; CHECK: umulh [[HI:x[0-9]+]], x0, x2
7 ; CHECK: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
13 ; CHECK-BE: umulh [[HI:x[0-9]+]], x1, x3
14 ; CHECK-BE: madd [[TEMP1:x[0-9]+]], x1, x2, [[HI]]
28 ; CHECK: umulh [[HI:x[0-9]+]], x0, x2
29 ; CHECK-NEXT: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
40 ; CHECK: umulh [[HI:x[0-9]+]], x0, x2
41 ; CHECK-NEXT: madd [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfAccelTable.cpp | 166 for (HashList::const_iterator HI = Buckets[i].begin(), in EmitHashes() local
168 HI != HE; ++HI) { in EmitHashes()
169 uint32_t HashValue = (*HI)->HashValue; in EmitHashes()
186 for (HashList::const_iterator HI = Buckets[i].begin(), in emitOffsets() local
188 HI != HE; ++HI) { in emitOffsets()
189 uint32_t HashValue = (*HI)->HashValue; in emitOffsets()
196 MCSymbolRefExpr::create((*HI)->Sym, Context), in emitOffsets()
209 for (HashList::const_iterator HI = Buckets[i].begin(), in EmitData() local
211 HI != HE; ++HI) { in EmitData()
214 if (PrevHash != UINT64_MAX && PrevHash != (*HI)->HashValue) in EmitData()
[all …]
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | fcanonicalize.ll | 190 ; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}}
191 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
200 ; GCN-DAG: v_bfrev_b32_e32 v[[HI:[0-9]+]], 1{{$}}
201 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
210 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x3ff00000{{$}}
211 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
220 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0xbff00000{{$}}
221 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
230 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x40300000{{$}}
231 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
[all …]
|
| D | zext-i64-bit-operand.ll | 4 ; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
7 ; GCN-NOT: v[[HI]]
11 ; GCN-NOT: v[[HI]]
13 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
24 ; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
27 ; GCN-NOT: v[[HI]]
30 ; GCN-NOT: v[[HI]]
33 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
|
| D | fract.f64.ll | 12 ; SI-DAG: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
16 ; SI-DAG: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
18 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
19 ; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]{{\]}}, -v{{\[}}[[RESLO]]:[[RESHI]…
20 ; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]{{\]}}, -[[SUB0]]
39 ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
43 ; SI-DAG: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
45 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
46 ; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO]]:[[HI]]{{\]}}, -v{{\[}}[[RESLO]]:[[RESHI…
47 ; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO]]:[[HI]]{{\]}}, -[[SUB0]]
[all …]
|
| D | shift-i64-opts.ll | 9 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
10 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
21 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
22 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
33 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
34 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
44 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
45 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
57 ; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
58 ; GCN: v_bfe_u32 v[[BFE:[0-9]+]], v[[HI]], 8, 23
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | zext-i64-bit-operand.ll | 4 ; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
7 ; GCN-NOT: v[[HI]]
11 ; GCN-NOT: v[[HI]]
13 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
24 ; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
27 ; GCN-NOT: v[[HI]]
30 ; GCN-NOT: v[[HI]]
33 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
|
| D | store-hi16.ll | 2 …achineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GFX906,NO-D16-HI %s
3 …achineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GFX803,NO-D16-HI %s
10 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
30 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
50 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
69 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
89 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
203 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
204 ; NO-D16-HI-NEXT: flat_store_short v[0:1], v2
221 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
[all …]
|
| D | fract.f64.ll | 12 ; SI-DAG: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
16 ; SI-DAG: v_cmp_class_f64_e64 vcc, v{{\[}}[[LO]]:[[HI]]], 3
18 ; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc
19 ; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]{{\]}}, -v{{\[}}[[RESLO]]:[[RESHI]…
20 ; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]{{\]}}, -[[SUB0]]
39 ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
43 ; SI-DAG: v_cmp_class_f64_e64 vcc, v{{\[}}[[LO]]:[[HI]]], 3
45 ; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc
46 ; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO]]:[[HI]]{{\]}}, -v{{\[}}[[RESLO]]:[[RESHI…
47 ; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO]]:[[HI]]{{\]}}, -[[SUB0]]
[all …]
|
| D | llvm.amdgcn.buffer.load.format.d16.ll | 14 ; UNPACKED: buffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+…
15 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
27 ; UNPACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9…
28 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
30 ; PACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]+…
31 ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
|
| D | fcanonicalize.ll | 273 ; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}}
274 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
283 ; GCN-DAG: v_bfrev_b32_e32 v[[HI:[0-9]+]], 1{{$}}
284 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
293 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x3ff00000{{$}}
294 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
303 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0xbff00000{{$}}
304 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
313 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x40300000{{$}}
314 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
[all …]
|
| D | shift-i64-opts.ll | 9 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
10 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
21 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
22 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
33 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
34 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
44 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
45 ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
57 ; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
58 ; GCN: v_bfe_u32 v[[BFE:[0-9]+]], v[[HI]], 8, 23
[all …]
|
| D | llvm.amdgcn.tbuffer.load.d16.ll | 14 ; UNPACKED: tbuffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]…
15 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
27 ; UNPACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-…
28 ; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
30 ; PACKED: tbuffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, off, s[{{[0-9]+:[0-9]…
31 ; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
|
| D | addrspacecast.ll | 14 ; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
26 ; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
30 ; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]]
55 ; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
68 ; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
72 ; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]]
170 ; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]]
173 ; GFX9-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]]
175 ; GFX9-XXX: v_mov_b32_e32 v[[HI:[0-9]+]], src_shared_base
179 ; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | fp128-bitcast-after-operation.ll | 14 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
16 ; PPC64-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0
17 ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
23 ; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
24 ; PPC64-P8-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0
25 ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
53 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
56 ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
62 ; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
66 ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
[all …]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | fp128-bitcast-after-operation.ll | 16 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
18 ; PPC64: and [[FLIP_BIT:[0-9]+]], [[HI]], [[MASK_REG]]
19 ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
25 ; PPC64-P8-DAG: mfvsrd [[HI:[0-9]+]], 1
28 ; PPC64-P8: and [[FLIP_BIT:[0-9]+]], [[HI]], [[SHIFT_REG]]
29 ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
58 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
61 ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
67 ; PPC64-P8-DAG: mfvsrd [[HI:[0-9]+]], 1
71 ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
[all …]
|
| /external/pdfium/core/fxcodec/jbig2/ |
| D | JBig2_TrdProc.cpp | 167 uint32_t HI = IBI->height(); in decode_Huffman() local
173 CURS += HI - 1; in decode_Huffman()
188 SBREG->composeFrom(SI, TI - HI + 1, IBI.Get(), SBCOMBOP); in decode_Huffman()
191 SBREG->composeFrom(SI - WI + 1, TI - HI + 1, IBI.Get(), SBCOMBOP); in decode_Huffman()
203 SBREG->composeFrom(TI, SI - HI + 1, IBI.Get(), SBCOMBOP); in decode_Huffman()
206 SBREG->composeFrom(TI - WI + 1, SI - HI + 1, IBI.Get(), SBCOMBOP); in decode_Huffman()
215 CURS += HI - 1; in decode_Huffman()
360 uint32_t HI = pIBI->height(); in decode_Arith() local
366 CURS += HI - 1; in decode_Arith()
381 SBREG->composeFrom(SI, TI - HI + 1, pIBI.Get(), SBCOMBOP); in decode_Arith()
[all …]
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| /external/icu/icu4c/source/data/translit/ |
| D | blt_blt_FONIPA.txt | 39 $HI = [ꪁ ꪃ ꪅ ꪇ ꪉ ꪋ ꪍ ꪏ ꪑ ꪓ ꪕ ꪗ ꪙ ꪛ ꪝ ꪟ ꪡ ꪣ ꪥ ꪧ ꪩ ꪫ ꪭ ꪯ];
40 $C = [$LO $HI];
62 $HI $W? $V12 {($CHK)} → $1 ˦; # Tone class 5: High-mid tone
63 $HI $W? {($V3 $CHK)} → $1 ˦; # Tone class 5: High-mid tone
69 $HI $W? { \uAABF ($V3 $F?)} → $1 ˦; # Tone class 5: High-mid tone
70 $HI $W? { \uAAC1 ($V3 $F?)} → $1 ˧˩; # Tone class 6: Mid-falling tone
76 $HI $W? $V12 { \uAABF ($F?)} → $1 ˦; # Tone class 5: High-mid tone
77 $HI $W? $V12 { \uAAC1 ($F?)} → $1 ˧˩; # Tone class 6: Mid-falling tone
80 {($HI $W? $V123 $F?)} $NOT_IPA_TONE → $1 ˥; # Tone class 4: High tone.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Utils/ |
| D | ARMBaseInfo.h | 40 HI, // Unsigned higher Greater than, or unordered enumerator
60 case HI: return LS; in getOppositeCondition()
61 case LS: return HI; in getOppositeCondition()
80 case ARMCC::HI: return "hi"; in ARMCondCodeToString()
103 .Case("hi", ARMCC::HI) in ARMCondCodeFromString()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/ |
| D | parse-pound-hi.s | 5 memw(gp+#HI) = r3
7 r3 = memw(gp+#HI)
37 r16.h = #HI(0x405000)
39 r16.h = #HI (0x405000)
55 r19.h = #HI(-559030611)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | AsmPrinter.cpp | 490 for (const HandlerInfo &HI : Handlers) { in EmitGlobalVariable() local
491 NamedRegionTimer T(HI.TimerName, HI.TimerDescription, in EmitGlobalVariable()
492 HI.TimerGroupName, HI.TimerGroupDescription, in EmitGlobalVariable()
494 HI.Handler->setSymbolSize(GVSym, Size); in EmitGlobalVariable()
710 for (const HandlerInfo &HI : Handlers) { in EmitFunctionHeader() local
711 NamedRegionTimer T(HI.TimerName, HI.TimerDescription, HI.TimerGroupName, in EmitFunctionHeader()
712 HI.TimerGroupDescription, TimePassesIsEnabled); in EmitFunctionHeader()
713 HI.Handler->beginFunction(MF); in EmitFunctionHeader()
1070 for (const HandlerInfo &HI : Handlers) { in EmitFunctionBody() local
1071 NamedRegionTimer T(HI.TimerName, HI.TimerDescription, in EmitFunctionBody()
[all …]
|