Searched refs:HI32 (Results 1 – 9 of 9) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZOperands.td | 65 def HI32 : SDNodeXForm<imm, [{
168 }], HI32>;
179 }], HI32>;
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| D | SystemZInstrInfo.td | 1111 (OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>;
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| /external/capstone/arch/Mips/ |
| D | MipsGenRegisterInfo.inc | 1246 // HI32 Register Class...
1247 static MCPhysReg HI32[] = {
1251 // HI32 Bit set.
1502 { "HI32", HI32, HI32Bits, 1, sizeof(HI32Bits), Mips_HI32RegClassID, 4, 4, 1, 1 },
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 1752 SDValue HI32; in LowerV2I64Splat() local
1767 HI32 = DAG.getNode(ISD::BITCAST, dl, OpVT, in LowerV2I64Splat()
1775 LO32 = HI32; in LowerV2I64Splat()
1777 HI32 = LO32; in LowerV2I64Splat()
1805 return DAG.getNode(SPUISD::SHUFB, dl, OpVT, HI32, LO32, in LowerV2I64Splat()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterInfo.inc | 2202 // HI32 Register Class...
2203 const MCPhysReg HI32[] = {
2207 // HI32 Bit set.
2652 { HI32, HI32Bits, 45, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 4, 1, true },
3917 { 32, 32, 32, VTLists+0 }, // HI32
6618 { // HI32
7124 {1, 1}, // HI32
7184 "HI32",
7217 2, // 3: HI32
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| D | MipsGenAsmMatcher.inc | 1918 MCK_HI32, // register class 'HI32'
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| /external/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 419 def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 434 def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.td | 353 def HI32 : SDNodeXForm<imm, [{
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