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Searched refs:HSUB (Results 1 – 14 of 14) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h336 X86_INTRINSIC_DATA(avx2_phsub_d, INTR_TYPE_2OP, X86ISD::HSUB, 0),
337 X86_INTRINSIC_DATA(avx2_phsub_w, INTR_TYPE_2OP, X86ISD::HSUB, 0),
1239 X86_INTRINSIC_DATA(ssse3_phsub_d_128, INTR_TYPE_2OP, X86ISD::HSUB, 0),
1240 X86_INTRINSIC_DATA(ssse3_phsub_w_128, INTR_TYPE_2OP, X86ISD::HSUB, 0),
DX86ScheduleZnver1.td1100 // HADD, HSUB PS/PD
1447 // HADD, HSUB PS/PD
DX86ISelLowering.h242 HSUB, enumerator
DX86InstrFragmentsSIMD.td62 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
DX86ISelLowering.cpp7836 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1); in LowerToHorizontalOp()
7872 X86Opcode = X86ISD::HSUB; in LowerToHorizontalOp()
7902 X86Opcode = X86ISD::HSUB; in LowerToHorizontalOp()
25950 case X86ISD::HSUB: return "X86ISD::HSUB"; in getTargetNodeName()
30638 Opcode0 == X86ISD::FHSUB || Opcode0 == X86ISD::HSUB || in combineTargetShuffle()
31139 HOp.getOpcode() != X86ISD::HSUB && HOp.getOpcode() != X86ISD::FHSUB) in foldShuffleOfHorizOp()
39242 return DAG.getNode(X86ISD::HSUB, DL, Ops[0].getValueType(), Ops); in combineSub()
/external/llvm/lib/Target/X86/
DX86ISelLowering.h231 HSUB, enumerator
DX86IntrinsicsInfo.h289 X86_INTRINSIC_DATA(avx2_phsub_d, INTR_TYPE_2OP, X86ISD::HSUB, 0),
290 X86_INTRINSIC_DATA(avx2_phsub_w, INTR_TYPE_2OP, X86ISD::HSUB, 0),
1944 X86_INTRINSIC_DATA(ssse3_phsub_d_128, INTR_TYPE_2OP, X86ISD::HSUB, 0),
1945 X86_INTRINSIC_DATA(ssse3_phsub_w_128, INTR_TYPE_2OP, X86ISD::HSUB, 0),
DX86InstrFragmentsSIMD.td68 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
DX86SchedHaswell.td1872 // HADD, HSUB PS/PD
DX86ISelLowering.cpp6406 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1); in LowerToHorizontalOp()
6442 X86Opcode = X86ISD::HSUB; in LowerToHorizontalOp()
6472 X86Opcode = X86ISD::HSUB; in LowerToHorizontalOp()
22132 case X86ISD::HSUB: return "X86ISD::HSUB"; in getTargetNodeName()
30811 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1); in combineSub()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td666 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v2i32|v4i16|v8i8)(_v.…
730 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v16i8|v2i64|v4i32|v8i…
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenAsmWriter.inc5881 "HADDPDrr\000HADDPSrm\000HADDPSrr\000HLT\000HSUBPDrm\000HSUBPDrr\000HSUB"
DX86GenAsmWriter1.inc6624 "HADDPDrr\000HADDPSrm\000HADDPSrr\000HLT\000HSUBPDrm\000HSUBPDrr\000HSUB"
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc9573 // FastEmit functions for X86ISD::HSUB.
12008 case X86ISD::HSUB: return fastEmit_X86ISD_HSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);