| /external/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-virtexts.arm.txt | 3 # HVC (ARM)
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-virtexts.arm.txt | 3 # HVC (ARM)
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| /external/u-boot/arch/arm/cpu/armv7/ |
| D | nonsec_virt.S | 81 orreq r5, r5, #0x100 @ allow HVC instruction
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 761 HVC = ExceptionFixed | 0x00000002, enumerator
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| D | disasm-arm64.cc | 1287 case HVC: mnemonic = "hvc"; break; in VisitException()
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 744 HVC = ExceptionFixed | 0x00000002, enumerator
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| D | disasm-aarch64.cc | 2152 case HVC: in VisitException()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedFalkorDetails.td | 1246 def : InstRW<[FalkorWr_1none_0cyc], (instrs BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, ISB, SMC, S…
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| D | AArch64SchedKryoDetails.td | 478 (instrs BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, ISB, HINT, SMC, SVC)>;
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| D | AArch64InstrInfo.td | 1487 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57.td | 129 "(t2|t)?HINT$", "(t)?HLT$", "(t2)?HVC$", "(t2)?ISB$", "ITasm$",
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| D | ARMInstrInfo.td | 2577 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2582 // Even though HVC isn't predicable, it's encoding includes a condition field.
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| D | ARMInstrThumb2.td | 3849 // Alias for HVC without the ".w" optional width specifier
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmWriter.inc | 1124 828638U, // HVC
4344 0U, // HVC
7183 // BKPT, BL, BLX, BLXi, BX, CPS1p, ERET, HLT, HVC, RFEDA, RFEDB, RFEIA, R...
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| D | ARMGenMCCodeEmitter.inc | 617 UINT64_C(3779068016), // HVC
8253 case ARM::HVC: {
11890 Feature_IsARM | Feature_HasVirtualization | 0, // HVC = 604
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedKryoDetails.td | 478 (instrs BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, ISB, HINT, SMC, SVC)>;
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| D | AArch64InstrInfo.td | 1280 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
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| /external/capstone/arch/AArch64/ |
| D | AArch64GenAsmWriter.inc | 736 21258U, // HVC
3128 0U, // HVC
5230 // BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, SMC, SVC
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 2467 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2472 // Even though HVC isn't predicable, it's encoding includes a condition field.
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| D | ARMInstrThumb2.td | 3859 // Alias for HVC without the ".w" optional width specifier
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 433 case ARM::HVC: { in checkDecodedInstruction()
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 422 case ARM::HVC: { in checkDecodedInstruction()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenMCCodeEmitter.inc | 1792 UINT64_C(3556769794), // HVC
11887 case AArch64::HVC:
13844 0, // HVC = 1779
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| D | AArch64GenAsmWriter.inc | 2591 75574U, // HVC
7110 0U, // HVC
9901 // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC
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| D | AArch64GenAsmWriter1.inc | 3540 150805U, // HVC
8059 0U, // HVC
10850 // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC
|