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Searched refs:HalfVT (Results 1 – 24 of 24) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DValueTypes.h298 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT() local
299 if (HalfVT.getSizeInBits() * 2 >= EVTSize) in getHalfSizedIntegerVT()
300 return HalfVT; in getHalfSizedIntegerVT()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DValueTypes.h333 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT() local
334 if (HalfVT.getSizeInBits() * 2 >= EVTSize) in getHalfSizedIntegerVT()
335 return HalfVT; in getHalfSizedIntegerVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp1560 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); in LowerUDIVREM64() local
1562 SDValue One = DAG.getConstant(1, DL, HalfVT); in LowerUDIVREM64()
1563 SDValue Zero = DAG.getConstant(0, DL, HalfVT); in LowerUDIVREM64()
1567 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero); in LowerUDIVREM64()
1568 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, One); in LowerUDIVREM64()
1571 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero); in LowerUDIVREM64()
1572 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, One); in LowerUDIVREM64()
1577 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
1608 SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2); in LowerUDIVREM64()
1609 SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc); in LowerUDIVREM64()
[all …]
DSIISelLowering.cpp4321 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), 2); in lowerBUILD_VECTOR() local
4325 SDValue Lo = DAG.getBuildVector(HalfVT, SL, in lowerBUILD_VECTOR()
4327 SDValue Hi = DAG.getBuildVector(HalfVT, SL, in lowerBUILD_VECTOR()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DValueTypes.h630 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT() local
631 if (HalfVT.getSizeInBits() * 2 >= EVTSize) in getHalfSizedIntegerVT()
632 return HalfVT; in getHalfSizedIntegerVT()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp1341 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); in LowerUDIVREM64() local
1343 SDValue one = DAG.getConstant(1, DL, HalfVT); in LowerUDIVREM64()
1344 SDValue zero = DAG.getConstant(0, DL, HalfVT); in LowerUDIVREM64()
1348 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero); in LowerUDIVREM64()
1349 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one); in LowerUDIVREM64()
1352 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero); in LowerUDIVREM64()
1353 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one); in LowerUDIVREM64()
1359 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
1371 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo); in LowerUDIVREM64()
1372 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo); in LowerUDIVREM64()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InterleavedAccess.cpp364 MVT HalfVT = scaleVectorType(VT); in interleave8bitStride4() local
382 createUnpackShuffleMask<uint32_t>(HalfVT, MaskLowTemp, true, false); in interleave8bitStride4()
383 createUnpackShuffleMask<uint32_t>(HalfVT, MaskHighTemp, false, false); in interleave8bitStride4()
DX86ISelLowering.cpp8712 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(), in LowerAVXCONCAT_VECTORS() local
8715 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, in LowerAVXCONCAT_VECTORS()
8717 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, in LowerAVXCONCAT_VECTORS()
8843 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(), in LowerCONCAT_VECTORSvXi1() local
8846 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, in LowerCONCAT_VECTORSvXi1()
8848 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, in LowerCONCAT_VECTORSvXi1()
13339 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(), HalfNumElts); in lowerVectorShuffleWithUndefHalf() local
13350 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1, in lowerVectorShuffleWithUndefHalf()
13360 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1, in lowerVectorShuffleWithUndefHalf()
13437 return DAG.getUNDEF(HalfVT); in lowerVectorShuffleWithUndefHalf()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.cpp1099 EVT HalfVT = in SplitInteger() local
1101 SplitInteger(Op, HalfVT, HalfVT, Lo, Hi); in SplitInteger()
DLegalizeVectorTypes.cpp2181 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, in SplitVecOp_TruncateHelper() local
2183 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec); in SplitVecOp_TruncateHelper()
2184 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec); in SplitVecOp_TruncateHelper()
DDAGCombiner.cpp4002 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2); in visitANDLike() local
4008 TLI.isNarrowingProfitable(VT, HalfVT) && in visitANDLike()
4009 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) && in visitANDLike()
4010 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) && in visitANDLike()
4011 TLI.isTruncateFree(VT, HalfVT) && in visitANDLike()
4012 TLI.isZExtFree(HalfVT, VT)) { in visitANDLike()
4022 EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout()); in visitANDLike()
4023 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, HalfVT, in visitANDLike()
4026 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT); in visitANDLike()
4028 SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trunc, ShiftK); in visitANDLike()
[all …]
DSelectionDAGBuilder.cpp223 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts() local
227 PartVT, HalfVT, V); in getCopyFromParts()
229 RoundParts / 2, PartVT, HalfVT, V); in getCopyFromParts()
231 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
232 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
DTargetLowering.cpp1042 EVT HalfVT = Op.getOperand(0).getValueType(); in SimplifyDemandedBits() local
1043 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits(); in SimplifyDemandedBits()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeTypes.cpp1126 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), in SplitInteger() local
1128 SplitInteger(Op, HalfVT, HalfVT, Lo, Hi); in SplitInteger()
DLegalizeIntegerTypes.cpp589 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts/2); in PromoteIntRes_TRUNCATE() local
593 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp, in PromoteIntRes_TRUNCATE()
595 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp, in PromoteIntRes_TRUNCATE()
DSelectionDAGBuilder.cpp122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts() local
126 PartVT, HalfVT); in getCopyFromParts()
128 RoundParts / 2, PartVT, HalfVT); in getCopyFromParts()
130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.cpp1161 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), in SplitInteger() local
1163 SplitInteger(Op, HalfVT, HalfVT, Lo, Hi); in SplitInteger()
DDAGCombiner.cpp2971 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2); in visitANDLike() local
2977 TLI.isNarrowingProfitable(VT, HalfVT) && in visitANDLike()
2978 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) && in visitANDLike()
2979 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) && in visitANDLike()
2980 TLI.isTruncateFree(VT, HalfVT) && in visitANDLike()
2981 TLI.isZExtFree(HalfVT, VT)) { in visitANDLike()
2991 EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout()); in visitANDLike()
2992 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, HalfVT, in visitANDLike()
2995 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT); in visitANDLike()
2997 SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trunc, ShiftK); in visitANDLike()
[all …]
DLegalizeVectorTypes.cpp1971 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, in SplitVecOp_TruncateHelper() local
1973 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec); in SplitVecOp_TruncateHelper()
1974 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec); in SplitVecOp_TruncateHelper()
DSelectionDAGBuilder.cpp154 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts() local
158 PartVT, HalfVT, V); in getCopyFromParts()
160 RoundParts / 2, PartVT, HalfVT, V); in getCopyFromParts()
162 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
163 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
DTargetLowering.cpp935 EVT HalfVT = Op.getOperand(0).getValueType(); in SimplifyDemandedBits() local
936 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits(); in SimplifyDemandedBits()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp6914 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(), in LowerAVXCONCAT_VECTORS() local
6919 concat128BitVectors(V1, V2, HalfVT, NumElems / 2, DAG, dl), in LowerAVXCONCAT_VECTORS()
6920 concat128BitVectors(V3, V4, HalfVT, NumElems / 2, DAG, dl), ResVT, in LowerAVXCONCAT_VECTORS()
6956 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(), in LowerCONCAT_VECTORSvXi1() local
6961 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops); in LowerCONCAT_VECTORSvXi1()
6965 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops); in LowerCONCAT_VECTORSvXi1()
10869 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(), HalfNumElts); in lowerVectorShuffleWithUndefHalf() local
10880 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1, in lowerVectorShuffleWithUndefHalf()
10890 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1, in lowerVectorShuffleWithUndefHalf()
10963 return DAG.getUNDEF(HalfVT); in lowerVectorShuffleWithUndefHalf()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp8792 EVT HalfVT = in split16BStores() local
8794 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, in split16BStores()
8796 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, in split16BStores()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp10063 EVT HalfVT = in splitStores() local
10065 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, in splitStores()
10067 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, in splitStores()